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diff --git a/solutions/baseline/gdn/gdn_decode_qk4_v8_d128_k_last/flashinfer_wrapper_9b7f1e.json b/solutions/baseline/gdn/gdn_decode_qk4_v8_d128_k_last/flashinfer_wrapper_9b7f1e.json
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@@ -0,0 +1,25 @@
+{
+  "name": "flashinfer_wrapper_9b7f1e",
+  "definition": "gdn_decode_qk4_v8_d128_k_last",
+  "author": "flashinfer",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA H20",
+      "NVIDIA H100",
+      "NVIDIA H200"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "flashinfer"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import math\nimport torch\nfrom flashinfer.gdn_decode import gated_delta_rule_decode_pretranspose\n\n\ndef run(q, k, v, state, A_log, a, dt_bias, b, scale):\n    if isinstance(scale, torch.Tensor):\n        scale = float(scale.item())\n    else:\n        scale = float(scale)\n    if scale == 0.0:\n        scale = 1.0 / math.sqrt(q.shape[-1])\n\n    B, T, num_v_heads, head_size = v.shape\n    output = torch.empty(B, T, num_v_heads, head_size, dtype=q.dtype, device=q.device)\n\n    out, new_state = gated_delta_rule_decode_pretranspose(\n        q=q,\n        k=k,\n        v=v,\n        state=state,\n        A_log=A_log,\n        a=a,\n        dt_bias=dt_bias,\n        b=b,\n        scale=scale,\n        output=output,\n        use_qk_l2norm=False,\n    )\n\n    return out, new_state\n"
+    }
+  ],
+  "description": "Solution using FlashInfer gated_delta_rule_decode_pretranspose for GDN single-token decode (qk4_v8_d128, k-last state layout)."
+}
diff --git a/solutions/baseline/gdn/gdn_prefill_qk4_v8_d128_k_last/flashinfer_wrapper_123ca6.json b/solutions/baseline/gdn/gdn_prefill_qk4_v8_d128_k_last/flashinfer_wrapper_123ca6.json
new file mode 100644
index 0000000000000000000000000000000000000000..908289d8b092e4321776d4522bc037f5d326bbe9
--- /dev/null
+++ b/solutions/baseline/gdn/gdn_prefill_qk4_v8_d128_k_last/flashinfer_wrapper_123ca6.json
@@ -0,0 +1,40 @@
+{
+  "name": "flashinfer_wrapper_123ca6",
+  "definition": "gdn_prefill_qk4_v8_d128_k_last",
+  "author": "flashinfer",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA B200"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "cutlass",
+      "cuda-python"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nimport torch.nn.functional as F\nfrom .gdn_blackwell.gdn import chunk_gated_delta_rule\n\n\ndef run(q, k, v, state, A_log, a, dt_bias, b, cu_seqlens, scale):\n    x = a.float() + dt_bias.float()\n    # Gate values in log-space: log(exp(-exp(A_log) * softplus(x))) = -exp(A_log) * softplus(x)\n    g = -torch.exp(A_log.float()) * F.softplus(x)\n    beta = torch.sigmoid(b.float())\n\n    varlen = cu_seqlens is not None and q.dim() == 3\n    if varlen:\n        q = q.unsqueeze(0)\n        k = k.unsqueeze(0)\n        v = v.unsqueeze(0)\n\n    output, new_state = chunk_gated_delta_rule(\n        q=q,\n        k=k,\n        v=v,\n        g=g,\n        beta=beta,\n        scale=None,\n        initial_state=state,\n        output_final_state=True,\n        cu_seqlens=cu_seqlens,\n        use_qk_l2norm_in_kernel=False,\n    )\n\n    if varlen:\n        output = output.squeeze(0)\n\n    return output, new_state\n"
+    },
+    {
+      "path": "gdn_blackwell/__init__.py",
+      "content": "# Blackwell GDN kernel package\n"
+    },
+    {
+      "path": "gdn_blackwell/gdn.py",
+      "content": "\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n  http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\n# Gated Delta Networks (GDN) chunked linear attention kernel for NVIDIA Blackwell (SM100).\n#\n# Implements the Chunk-wise Gated Delta Rule linear attention using CuTe-DSL,\n# for Blackwell Architecture.\n#\n# Key Features:\n#   - Supports Persistent & Non-persistent modes\n#   - Supports fixed-length and variable-length sequences (cu_seqlens)\n#   - Supports grouped value attention (GVA) where h_v is a multiple of h_q\n#   - Supports head dimension (128)\n#   - Supports input data types (f16/bf16)\n#   - Supports output data types (f16/bf16)\n#   - Supports initial_state to provide the initial state\n#   - Supports output_final_state flag to return the final state\n#   - State input and output are in f32 (fp16/bf16 not supported yet)\n\nimport torch\n\nfrom typing import Optional, Type, Tuple, Union\n\nimport cutlass\nimport cutlass.cute as cute\nimport cutlass.utils as utils\nimport cutlass.pipeline as pipeline\nimport cutlass.cute.nvgpu.tcgen05 as tcgen05\nimport cutlass.utils.blackwell_helpers as sm100_utils\nfrom cutlass.cute.runtime import from_dlpack\nfrom cutlass._mlir.dialects import nvvm\n\nimport cuda.bindings.driver as cuda\n\n\nfrom .gdn_tile_scheduler import *\nfrom .gdn_helpers import *\n\nimport functools\nimport warnings\n\nfrom cutlass.cute import EnableTVMFFI\n\n\ndef make_thread_cooperative_group(size: Int32):\n    # return pipeline.CooperativeGroup(pipeline.Agent.Thread, size, size) # old version\n    return pipeline.CooperativeGroup(pipeline.Agent.Thread, size)\n\n\nclass GDN:\n    \"\"\"Blackwell (SM100) kernel for Chunk-wise Gated Delta Rule linear attention.\"\"\"\n\n    def __init__(\n        self,\n        is_persistent: bool = False,\n        chunk_size: Int32 = 128,  # Only 128 is supported in current version\n        head_dim: Int32 = 128,  # Only 128 is supported in current version\n    ):\n        self.chunk_size = chunk_size\n        self.is_persistent = is_persistent\n\n        self.head_dim = head_dim\n        self.cta_tiler = (chunk_size, chunk_size, head_dim)\n        self.gate_tiler = (chunk_size, 1)\n        self.beta_tiler = (chunk_size, 1)\n        self.state_output_tiler = (head_dim, head_dim)\n        self.o_output_tiler = (chunk_size, head_dim)\n\n        self.g_beta_dtype = cutlass.Float32\n        self.acc_dtype = cutlass.Float32\n        self.state_dtype = cutlass.Float32\n\n        self.mma_tiler = (chunk_size, chunk_size, head_dim)\n        self.qk_mma_tiler = self.mma_tiler\n        self.kkt_mma_tiler = self.mma_tiler\n        self.kst_mma_tiler = self.mma_tiler\n        self.tuw_mma_tiler = self.mma_tiler\n        self.o_intra_mma_tiler = (chunk_size, head_dim, chunk_size)\n        self.qs_mma_tiler = (chunk_size, head_dim, head_dim)\n        self.update_s_mma_tiler = (head_dim, head_dim, chunk_size)\n\n        self.epi_tile = (128, 128)\n\n        self.cluster_shape_mnk = (1, 1, 1)\n\n        self.buffer_align_bytes = 1024\n\n        self.q_stage = 1\n        self.one_stage = 1\n        self.kv_stage = 1\n        self.qk_stage = 2\n        self.gate_stage = 1\n        self.beta_stage = 1\n        self.mma_cudacore_stage = 1\n        self.mma_qk_stage = 2\n        self.epi_stage = 1\n\n        self.cudacore_warp_ids = (0, 1, 2, 3)\n        self.mma_warp_id = 4\n        self.load_warp_id = 5\n        self.epilogue_warp_id = 6\n        self.gb_warp_id = 7\n\n        self.threads_per_warp = 32\n        self.threads_per_cta = self.threads_per_warp * len(\n            (\n                *self.cudacore_warp_ids,\n                self.mma_warp_id,\n                self.load_warp_id,\n                self.epilogue_warp_id,\n                self.gb_warp_id,\n            )\n        )\n\n        # TMEM configuration\n        SM100_TMEM_CAPACITY_COLUMNS = 512\n        self.tmem_alloc_cols = SM100_TMEM_CAPACITY_COLUMNS\n        self.tmem_kkt_output = 0\n        self.tmem_qkt_output = 384\n        self.tmem_gate_qk = 384\n        self.tmem_gate_q = 448  # 448\n        self.tmem_k_input = 64\n        self.tmem_kst_output = 256\n        self.tmem_ivt_ss_l0_output = 448\n        self.tmem_ivt_ts_l0_input = 320\n        self.tmem_ivt_ts_l0_output = 448\n        self.tmem_ivt_ss_l1_output = 320\n        self.tmem_ivt_ts_l1_input = 320\n        self.tmem_ivt_ts_l1_output = 256\n        self.tmem_tuw_output = 256\n        self.tmem_o_intra_output = 256\n        self.tmem_o_inter_output = 256\n        self.tmem_update_s_output = 128\n        self.tmem_gamma = 256\n\n        self.tmem_state = 128\n\n        # Registers configuration\n        self.num_regs_cudacore = 240\n        self.num_regs_mma = 64\n        self.num_regs_other = 64\n        self.num_regs_gb = 64\n\n        # Named barrier IDs\n        self.cta_sync_bar_id = 0\n        self.tmem_alloc_sync_bar_id = 1\n        self.cudacore_mma_sync_bar_id = 2\n        self.wg_sync_bar_id = 3\n        self.epi_load_sync_bar_id = 4\n\n        # Matrix inversion using TFloat32\n        self.invert_type_ab = cutlass.TFloat32\n        self.invert_acc_type = cutlass.Float32\n        self.invert_mma_sub_l0_tiler = (64, 64, 32)\n        self.invert_mma_sub_l1_tiler = (64, 64, 64)\n        self.invert_mma_tiler = (128, 128, 64)\n        self.invert_sub_stage = 1\n        self.sub_stage = 9\n\n    @staticmethod\n    def can_implement(\n        q_shape: Tuple[int, int, int, int] | Tuple[int, Tuple[int, ...], int, int],\n        v_shape: Tuple[int, int, int, int] | Tuple[int, Tuple[int, ...], int, int],\n        in_dtype: Type[cutlass.Numeric],\n        out_dtype: Type[cutlass.Numeric],\n        g_beta_dtype: Type[cutlass.Numeric],\n        use_qk_l2norm_in_kernel: bool = False,\n    ) -> bool:\n        \"\"\"\n        Check if the gdn can be implemented\n        \"\"\"\n\n        can_implement = True\n\n        # Unpack parameters\n        b, s_q, h_q, d = q_shape\n        b_, _, h_v, d_ = v_shape\n\n        if use_qk_l2norm_in_kernel:\n            warnings.warn(\"use_qk_l2norm_in_kernel is not supported yet\", stacklevel=2)\n            can_implement = False\n\n        if b != b_:\n            warnings.warn(\"q & k must have the same batch size\", stacklevel=2)\n            can_implement = False\n\n        if d != d_:\n            warnings.warn(\"q & k must have the same head dimension\", stacklevel=2)\n            can_implement = False\n\n        # todo: maybe support more later.\n        if d not in {128}:\n            warnings.warn(\"head dimension must be 128\", stacklevel=2)\n            can_implement = False\n\n        if h_v % h_q != 0:\n            warnings.warn(\"h_v must be divisible by h_q\", stacklevel=2)\n\n            can_implement = False\n\n        if isinstance(s_q, tuple) and len(s_q) != b:\n            warnings.warn(\n                \"variable_seqlen s_q must have the length of batch size\", stacklevel=2\n            )\n            can_implement = False\n\n        if in_dtype not in {\n            cutlass.BFloat16,\n            cutlass.Float16,\n            torch.float16,\n            torch.bfloat16,\n        }:\n            warnings.warn(\n                \"in_dtype must be BFloat16 or Float16 or torch.float16 or torch.bfloat16\",\n                stacklevel=2,\n            )\n            can_implement = False\n\n        if out_dtype not in {\n            cutlass.BFloat16,\n            cutlass.Float16,\n            torch.float16,\n            torch.bfloat16,\n        }:\n            warnings.warn(\n                \"out_dtype must be BFloat16 or Float16 or torch.float16 or torch.bfloat16\",\n                stacklevel=2,\n            )\n            can_implement = False\n\n        if g_beta_dtype not in {cutlass.Float32, torch.float32}:\n            warnings.warn(\n                \"g_beta_dtype must be Float32 or torch.float32, but got {}\".format(\n                    g_beta_dtype\n                ),\n                stacklevel=2,\n            )\n            can_implement = False\n\n        return can_implement\n\n    @cute.kernel\n    def kernel(\n        self,\n        qk_tiled_mma: cute.TiledMma,\n        o_intra_tiled_mma: cute.TiledMma,\n        o_intra_tiled_ts_mma_new: cute.TiledMma,\n        qs_tiled_mma: cute.TiledMma,\n        update_s_tiled_mma: cute.TiledMma,\n        kkt_tiled_mma: cute.TiledMma,\n        kst_tiled_mma: cute.TiledMma,\n        fake_state_tiled_mma: cute.TiledMma,\n        invert_sub_tiled_mma_ss_l0: cute.TiledMma,\n        invert_sub_tiled_mma_ts_l0: cute.TiledMma,\n        invert_sub_tiled_mma_ss_l1: cute.TiledMma,\n        invert_sub_tiled_mma_ts_l1: cute.TiledMma,\n        tuw_tiled_mma: cute.TiledMma,\n        tma_atom_q: cute.CopyAtom,\n        mQ_qdl: cute.Tensor,\n        tma_atom_k: cute.CopyAtom,\n        mK_kdl: cute.Tensor,\n        tma_atom_v: cute.CopyAtom,\n        mV_dkl: cute.Tensor,\n        tma_atom_state_f32: Optional[cute.CopyAtom],\n        mState_f32: Optional[cute.Tensor],\n        gate: cute.Tensor,\n        beta: cute.Tensor,\n        O: cute.Tensor,\n        tma_atom_state_output: Optional[cute.CopyAtom],\n        mStateOutput: Optional[cute.Tensor],\n        tma_atom_o_output: cute.CopyAtom,\n        mO_qdl: cute.Tensor,\n        cum_seqlen_q: Optional[cute.Tensor],\n        q_smem_layout_staged: cute.ComposedLayout,\n        k_smem_layout_staged: cute.ComposedLayout,\n        qk_smem_layout_staged: cute.ComposedLayout,\n        o_intra_smem_layout_staged_a: cute.ComposedLayout,\n        o_intra_smem_layout_staged_b: cute.ComposedLayout,\n        o_intra_smem_layout_staged_a_new: cute.ComposedLayout,\n        qs_smem_layout_staged_a: cute.ComposedLayout,\n        qs_smem_layout_staged_b: cute.ComposedLayout,\n        update_s_smem_layout_staged_a: cute.ComposedLayout,\n        update_s_smem_layout_staged_b: cute.ComposedLayout,\n        state_smem_layout_staged: cute.ComposedLayout,\n        state_smem_layout_f32_staged: cute.ComposedLayout,\n        state_output_smem_layout_staged: cute.ComposedLayout,\n        o_output_smem_layout_staged: cute.ComposedLayout,\n        gate_smem_layout_staged: cute.Layout,\n        beta_smem_layout_staged: cute.Layout,\n        ivt_smem_layout: cute.Layout,\n        sub_inner_smem_layout_staged: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ss_l0_a: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ss_l0_b: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ts_l0_a: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ts_l0_b: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ss_l1_a: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ss_l1_b: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ts_l1_a: cute.ComposedLayout,\n        invert_sub_smem_layout_staged_ts_l1_b: cute.ComposedLayout,\n        tuw_smem_layout_staged_a: cute.ComposedLayout,\n        tuw_smem_layout_staged_b: cute.ComposedLayout,\n        v_smem_layout_staged_b: cute.ComposedLayout,\n        scale: cutlass.Float32,\n        tile_sched_params: GdnStaticTileSchedulerParams,\n    ):\n        \"\"\"Warp-specialized GDN kernel entry point.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        warp_idx = cute.arch.make_warp_uniform(cute.arch.warp_idx())\n\n        # Prefetch TMA descriptors\n        if warp_idx == self.load_warp_id:\n            cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_q)\n            cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_k)\n            cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_v)\n            cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_o_output)\n            if cutlass.const_expr(tma_atom_state_f32 is not None):\n                cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_state_f32)\n            if cutlass.const_expr(tma_atom_state_output is not None):\n                cute.nvgpu.cpasync.prefetch_descriptor(tma_atom_state_output)\n\n        # Alloc\n        smem = utils.SmemAllocator()\n        storage = smem.allocate(self.shared_storage)\n\n        load_qk_producer, load_qk_consumer = pipeline.PipelineTmaUmma.create(\n            num_stages=self.qk_stage,\n            producer_group=make_thread_cooperative_group(len([self.load_warp_id])),\n            consumer_group=make_thread_cooperative_group(len([self.mma_warp_id])),\n            tx_count=self.tma_copy_kv_bytes,\n            barrier_storage=storage.load_qk_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        load_v_producer, load_v_consumer = pipeline.PipelineTmaAsync.create(\n            num_stages=self.one_stage,\n            producer_group=make_thread_cooperative_group(len([self.load_warp_id])),\n            consumer_group=make_thread_cooperative_group(\n                len(self.cudacore_warp_ids),\n            ),\n            tx_count=self.tma_copy_v_bytes,\n            barrier_storage=storage.load_v_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        load_state_producer, load_state_consumer = pipeline.PipelineTmaAsync.create(\n            num_stages=self.one_stage,\n            producer_group=make_thread_cooperative_group(len([self.load_warp_id])),\n            consumer_group=make_thread_cooperative_group(len(self.cudacore_warp_ids)),\n            tx_count=self.tma_copy_state_f32_bytes,\n            barrier_storage=storage.load_state_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        mma_qk_producer0, mma_qk_consumer0 = pipeline.PipelineUmmaAsync.create(\n            num_stages=self.mma_qk_stage,\n            producer_group=make_thread_cooperative_group(len([self.mma_warp_id])),\n            consumer_group=make_thread_cooperative_group(\n                self.threads_per_warp * len(self.cudacore_warp_ids)\n            ),\n            barrier_storage=storage.mma_qk_mbar_ptr0.data_ptr(),\n        ).make_participants()\n\n        mma_cudacore_producer0, mma_cudacore_consumer0 = (\n            pipeline.PipelineUmmaAsync.create(\n                num_stages=self.mma_cudacore_stage,\n                producer_group=make_thread_cooperative_group(len([self.mma_warp_id])),\n                consumer_group=make_thread_cooperative_group(\n                    self.threads_per_warp * len(self.cudacore_warp_ids)\n                ),\n                barrier_storage=storage.mma_cudacore_mbar_ptr0.data_ptr(),\n            ).make_participants()\n        )\n\n        gb_w0_producer, gb_w0_consumer = pipeline.PipelineAsync.create(\n            num_stages=self.gate_stage,\n            producer_group=make_thread_cooperative_group(self.threads_per_warp),\n            consumer_group=make_thread_cooperative_group(\n                self.threads_per_warp * len(self.cudacore_warp_ids)\n            ),\n            barrier_storage=storage.gb_w0_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        epi_w0_producer, epi_w0_consumer = pipeline.PipelineAsync.create(\n            num_stages=self.epi_stage,\n            producer_group=make_thread_cooperative_group(self.threads_per_warp),\n            consumer_group=make_thread_cooperative_group(\n                self.threads_per_warp * len(self.cudacore_warp_ids)\n            ),\n            barrier_storage=storage.epi_w0_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        w0_epi_producer, w0_epi_consumer = pipeline.PipelineAsync.create(\n            num_stages=self.epi_stage,\n            producer_group=make_thread_cooperative_group(\n                self.threads_per_warp * len(self.cudacore_warp_ids)\n            ),\n            consumer_group=make_thread_cooperative_group(self.threads_per_warp),\n            barrier_storage=storage.w0_epi_mbar_ptr.data_ptr(),\n        ).make_participants()\n\n        tmem_dealloc_mbar_ptr = storage.tmem_dealloc_mbar_ptr.data_ptr()\n\n        #  tmem barrier init\n        if warp_idx == self.gb_warp_id:\n            cute.arch.mbarrier_init(\n                tmem_dealloc_mbar_ptr,\n                self.threads_per_warp * len((*self.cudacore_warp_ids,)),\n            )\n        cute.arch.mbarrier_init_fence()\n\n        sQK = storage.sQK.get_tensor(\n            qk_smem_layout_staged.outer, swizzle=qk_smem_layout_staged.inner\n        )\n        sQ = cute.make_tensor(\n            cute.recast_ptr(\n                sQK[None, None, None, 1].iterator,\n                swizzle_=q_smem_layout_staged.inner,\n                dtype=self.i_dtype,\n            ),\n            q_smem_layout_staged.outer,\n        )\n        sK = cute.make_tensor(\n            cute.recast_ptr(\n                sQK[None, None, None, 0].iterator,\n                swizzle_=k_smem_layout_staged.inner,\n                dtype=self.i_dtype,\n            ),\n            k_smem_layout_staged.outer,\n        )\n        sStateInput = cute.make_tensor(\n            cute.recast_ptr(\n                storage.sState.data_ptr(),\n                swizzle_=state_smem_layout_staged.inner,\n                dtype=self.i_dtype,\n            ),\n            state_smem_layout_staged.outer,\n        )\n        sV = cute.make_tensor(\n            cute.recast_ptr(\n                storage.sV.data_ptr(),\n                swizzle_=v_smem_layout_staged_b.inner,\n                dtype=self.i_dtype,\n            ),\n            v_smem_layout_staged_b.outer,\n        )\n\n        sGate = storage.sGate.get_tensor(gate_smem_layout_staged)\n        sBeta = storage.sBeta.get_tensor(beta_smem_layout_staged)\n        sGateCumsum = storage.sGateCumsum.get_tensor(\n            cute.select(gate_smem_layout_staged, mode=[0, 1])\n        )\n        sSubInner = storage.sSubInner.get_tensor(sub_inner_smem_layout_staged)\n        sInvertSubSSL0A = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 6].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ss_l0_a.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ss_l0_a.outer,\n        )\n\n        sInvertSubSSL0B = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 7].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ss_l0_b.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ss_l0_b.outer,\n        )\n        sInvertSubTSL0B = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 8].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ts_l0_b.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ts_l0_b.outer,\n        )\n        sInvertSubSSL1A = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 0].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ss_l1_a.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ss_l1_a.outer,\n        )\n        sInvertSubSSL1B = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 2].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ss_l1_b.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ss_l1_b.outer,\n        )\n        sInvertSubTSL1B = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 6].iterator,\n                swizzle_=invert_sub_smem_layout_staged_ts_l1_b.inner,\n                dtype=self.invert_type_ab,\n            ),\n            invert_sub_smem_layout_staged_ts_l1_b.outer,\n        )\n\n        sInvertSubReg = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 4].iterator, dtype=self.invert_type_ab\n            ),\n            cute.make_layout(((4, 128), 8)),\n        )\n\n        sStateInputF32 = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 0].iterator,\n                swizzle_=state_smem_layout_f32_staged.inner,\n                dtype=self.state_dtype,\n            ),\n            state_smem_layout_f32_staged.outer,\n        )\n        sStateOutput = cute.make_tensor(\n            cute.recast_ptr(\n                sQK[None, None, None, 0].iterator,\n                swizzle_=state_output_smem_layout_staged.inner,\n                dtype=self.state_dtype,\n            ),\n            state_output_smem_layout_staged.outer,\n        )\n\n        sOIntraB = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 4].iterator,\n                swizzle_=o_intra_smem_layout_staged_b.inner,\n                dtype=self.i_dtype,\n            ),\n            o_intra_smem_layout_staged_b.outer,\n        )\n        sQSB = cute.make_tensor(\n            cute.recast_ptr(\n                storage.sState.data_ptr(),\n                swizzle_=qs_smem_layout_staged_b.inner,\n                dtype=self.i_dtype,\n            ),\n            qs_smem_layout_staged_b.outer,\n        )\n\n        sUpdateA = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 4].iterator,\n                swizzle_=update_s_smem_layout_staged_a.inner,\n                dtype=self.i_dtype,\n            ),\n            update_s_smem_layout_staged_a.outer,\n        )\n        sUpdateB = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 0].iterator,\n                swizzle_=update_s_smem_layout_staged_b.inner,\n                dtype=self.i_dtype,\n            ),\n            update_s_smem_layout_staged_b.outer,\n        )\n\n        sO = cute.make_tensor(\n            cute.recast_ptr(\n                storage.sState.data_ptr(),\n                swizzle_=o_output_smem_layout_staged.inner,\n                dtype=self.i_dtype,\n            ),\n            o_output_smem_layout_staged.outer,\n        )\n        sIvt = storage.sIvt.get_tensor(ivt_smem_layout)\n\n        sTuwA = cute.make_tensor(\n            cute.recast_ptr(\n                sSubInner[None, None, None, 0].iterator,\n                swizzle_=tuw_smem_layout_staged_a.inner,\n                dtype=self.i_dtype,\n            ),\n            tuw_smem_layout_staged_a.outer,\n        )\n        sTuwB = cute.make_tensor(\n            cute.recast_ptr(storage.sV.data_ptr(), dtype=self.k_dtype),\n            tuw_smem_layout_staged_b,\n        )\n        sTuwAStore_layout = cute.make_layout(\n            ((128, (4, 2)), 8), stride=((4, (1, 512)), 1024)\n        )\n        sTuwAStore = cute.make_tensor(\n            cute.recast_ptr(sTuwA.iterator, dtype=cutlass.Float32), sTuwAStore_layout\n        )\n\n        if warp_idx == self.epilogue_warp_id:\n            # Alloc tmem buffer\n            tmem_alloc_cols = cutlass.Int32(self.tmem_alloc_cols)\n            cute.arch.alloc_tmem(tmem_alloc_cols, storage.tmem_holding_buf)\n\n        # Ensure visibility of local mbarrier inits and tmem alloc\n        cute.arch.sync_threads()\n\n        tmem_ptr = cute.arch.retrieve_tmem_ptr(\n            self.acc_dtype,\n            alignment=16,\n            ptr_to_buffer_holding_addr=storage.tmem_holding_buf,\n        )\n\n        qk_thr_mma = qk_tiled_mma.get_slice(0)  # default 1sm\n        tSrQ = qk_thr_mma.make_fragment_A(sQK)\n        tSrK = qk_thr_mma.make_fragment_B(sQK)\n        qk_acc_shape = qk_thr_mma.partition_shape_C(\n            (self.qk_mma_tiler[0], self.qk_mma_tiler[1])\n        )\n        tQKtQK_fake = qk_thr_mma.make_fragment_C(qk_acc_shape)\n        tQKtQK = cute.make_tensor(tmem_ptr + self.tmem_qkt_output, tQKtQK_fake.layout)\n\n        kkt_thr_mma = kkt_tiled_mma.get_slice(0)  # default 1sm\n        tArK = kkt_thr_mma.make_fragment_A(sQK)\n        tArKT = kkt_thr_mma.make_fragment_B(sQK)\n        kkt_acc_shape = kkt_thr_mma.partition_shape_C(\n            (self.kkt_mma_tiler[0], self.kkt_mma_tiler[1])\n        )\n\n        fake_state_thr_mma = fake_state_tiled_mma.get_slice(0)\n\n        kst_thr_mma = kst_tiled_mma.get_slice(0)\n        tKSrK_0 = kst_thr_mma.make_fragment_A(sQK)\n        tKSrST = kst_thr_mma.make_fragment_B(sStateInput)\n        kst_acc_shape = kst_thr_mma.partition_shape_C(\n            (self.kst_mma_tiler[0], self.kst_mma_tiler[1])\n        )\n        tKStKS_fake = kst_thr_mma.make_fragment_C(kst_acc_shape)\n        tKStKS = cute.make_tensor(tmem_ptr + self.tmem_kst_output, tKStKS_fake.layout)\n        # input smem A\n        tKStK_layout = cute.composition(tKStKS.layout, cute.make_layout((128, 64)))\n        tKtK = cute.make_tensor(tmem_ptr + self.tmem_k_input, tKStK_layout)\n\n        invert_sub_thr_mma_ss_l0 = invert_sub_tiled_mma_ss_l0.get_slice(0)\n        tSrD = invert_sub_thr_mma_ss_l0.make_fragment_A(sInvertSubSSL0A)\n        tSrC = invert_sub_thr_mma_ss_l0.make_fragment_B(sInvertSubSSL0B)\n        invert_sub_acc_shape = invert_sub_thr_mma_ss_l0.partition_shape_C(\n            (self.invert_mma_sub_l0_tiler[0], self.invert_mma_sub_l0_tiler[1])\n        )\n\n        tKKTtKKT_fake = kkt_thr_mma.make_fragment_C(kkt_acc_shape)\n        tKKTtKKT = cute.make_tensor(\n            tmem_ptr + self.tmem_kkt_output, tKKTtKKT_fake.layout\n        )\n\n        tItSSL0_fake = invert_sub_thr_mma_ss_l0.make_fragment_C(invert_sub_acc_shape)\n        tItSSL0 = cute.make_tensor(\n            tmem_ptr + self.tmem_ivt_ss_l0_output, tItSSL0_fake.layout\n        )\n\n        # : ((128,128),1,1):((65536,1),0,0)\n        tQgate_layout = cute.make_layout(((128, 64), 1, 1), stride=((65536, 1), 0, 0))\n        tQgate = cute.make_tensor(tmem_ptr + self.tmem_gate_q, tQgate_layout)\n\n        tGamma_layout = cute.make_layout(((128, 128), 1, 1), stride=((65536, 1), 0, 0))\n        tGamma = cute.make_tensor(tmem_ptr + self.tmem_gamma, tGamma_layout)\n\n        # tStage\n        tStateF32_layout = cute.make_layout(\n            ((128, 128), 1, 1), stride=((65536, 1), 0, 0)\n        )\n        tStateF32 = cute.make_tensor(tmem_ptr + self.tmem_state, tStateF32_layout)\n\n        invert_sub_thr_mma_ts_l0 = invert_sub_tiled_mma_ts_l0.get_slice(0)\n        tInrDCL0A_fake = invert_sub_thr_mma_ts_l0.make_fragment_A(\n            invert_sub_smem_layout_staged_ts_l0_a.outer.shape\n        )\n        tInrDCL0A = cute.make_tensor(\n            cute.recast_ptr(\n                tmem_ptr,\n                dtype=tInrDCL0A_fake.element_type,\n            )\n            + self.tmem_ivt_ts_l0_input,\n            tInrDCL0A_fake.layout,\n        )\n\n        # input smem B\n        tSrDCL0B = invert_sub_thr_mma_ts_l0.make_fragment_B(sInvertSubTSL0B)\n\n        # output tmem C\n        tItTSL0_fake = invert_sub_thr_mma_ts_l0.make_fragment_C(invert_sub_acc_shape)\n        tItTSL0 = cute.make_tensor(\n            tmem_ptr + self.tmem_ivt_ts_l0_output, tItTSL0_fake.layout\n        )\n\n        invert_sub_thr_mma_ss_l1 = invert_sub_tiled_mma_ss_l1.get_slice(0)\n        tSrD_ivt_l1 = invert_sub_thr_mma_ss_l1.make_fragment_A(sInvertSubSSL1A)\n        tSrC_ivt_l1 = invert_sub_thr_mma_ss_l1.make_fragment_B(sInvertSubSSL1B)\n        invert_sub_acc_l1_shape = invert_sub_thr_mma_ss_l1.partition_shape_C(\n            (self.invert_mma_sub_l1_tiler[0], self.invert_mma_sub_l1_tiler[1])\n        )\n        tCtAcc_ivt_l1_ss_fake = invert_sub_thr_mma_ss_l1.make_fragment_C(\n            invert_sub_acc_l1_shape\n        )\n        tStO_ivt_l1_ss0 = cute.make_tensor(\n            tmem_ptr + self.tmem_ivt_ss_l1_output, tCtAcc_ivt_l1_ss_fake.layout\n        )\n\n        invert_sub_thr_mma_ts_l1 = invert_sub_tiled_mma_ts_l1.get_slice(0)\n        invert_acc_ts_l1_shape = invert_sub_thr_mma_ts_l1.partition_shape_C(\n            (self.invert_mma_sub_l1_tiler[0], self.invert_mma_sub_l1_tiler[1])\n        )\n        # output tmem C\n        tOtTSL1_fake = invert_sub_thr_mma_ts_l1.make_fragment_C(invert_acc_ts_l1_shape)\n        tOtTSL1 = cute.make_tensor(\n            tmem_ptr + self.tmem_ivt_ts_l1_output, tOtTSL1_fake.layout\n        )\n\n        tuw_thr_mma = tuw_tiled_mma.get_slice(0)\n        # input smem A\n        tTUWrA = tuw_thr_mma.make_fragment_A(sTuwA)\n        # input smem B\n        tTUWrB = tuw_thr_mma.make_fragment_B(sTuwB)\n        # output tmem C\n        tuw_acc_shape = tuw_thr_mma.partition_shape_C(\n            (self.tuw_mma_tiler[0], self.tuw_mma_tiler[1])\n        )\n        tVtTUW_fake = tuw_thr_mma.make_fragment_C(tuw_acc_shape)\n        tVtTUW = cute.make_tensor(tmem_ptr + self.tmem_tuw_output, tVtTUW_fake.layout)\n\n        o_intra_thr_mma = o_intra_tiled_mma.get_slice(0)\n        # input smem B\n        tOIntrarB = o_intra_thr_mma.make_fragment_B(sOIntraB)\n        # output tmem C\n        o_intra_acc_shape = o_intra_thr_mma.partition_shape_C(\n            (self.o_intra_mma_tiler[0], self.o_intra_mma_tiler[1])\n        )\n\n        o_intra_thr_mma_new = o_intra_tiled_ts_mma_new.get_slice(0)\n        # input smem A\n        tQKMtQKM_layout = cute.composition(tQKtQK.layout, cute.make_layout((128, 64)))\n        tQKMtQKM = cute.make_tensor(tmem_ptr + self.tmem_gate_qk, tQKMtQKM_layout)\n\n        update_s_thr_mma = update_s_tiled_mma.get_slice(0)\n        tUpdateA = update_s_thr_mma.make_fragment_A(sUpdateA)\n        tUpdateB = update_s_thr_mma.make_fragment_B(sUpdateB)\n        update_s_acc_shape = update_s_thr_mma.partition_shape_C(\n            (self.update_s_mma_tiler[0], self.update_s_mma_tiler[1])\n        )\n        tStUpdate_fake = update_s_thr_mma.make_fragment_C(update_s_acc_shape)\n        tStUpdate = cute.make_tensor(\n            tmem_ptr + self.tmem_update_s_output, tStUpdate_fake.layout\n        )\n\n        qs_thr_mma = qs_tiled_mma.get_slice(0)\n        tQSB = qs_thr_mma.make_fragment_B(sQSB)\n        qs_acc_shape = qs_thr_mma.partition_shape_C(\n            (self.qs_mma_tiler[0], self.qs_mma_tiler[1])\n        )\n        tOintertQS_fake = qs_thr_mma.make_fragment_C(qs_acc_shape)\n        tOintertQS = cute.make_tensor(\n            tmem_ptr + self.tmem_o_inter_output, tOintertQS_fake.layout\n        )\n\n        loop_count = cute.ceil_div(mO_qdl.shape[0], self.cta_tiler[0])\n\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  Load Gate Beta\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx == self.gb_warp_id:\n            cute.arch.setmaxregister_decrease(self.num_regs_gb)\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n            lane_id = tidx % 32\n\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n\n                batch_coord = curr_block_coord[2][1]\n                continue_cond = False\n                cuseqlen_q = Int32(0)\n                seqlen_q = mQ_qdl.shape[0]\n\n                head_coord = curr_block_coord[2][0]\n\n                if cutlass.const_expr(cum_seqlen_q is not None):\n                    cuseqlen_q = cum_seqlen_q[batch_coord]\n                    seqlen_q = cum_seqlen_q[batch_coord + 1] - cuseqlen_q\n                    continue_cond = (\n                        not GdnStaticTileScheduler.check_valid_work_for_seqlen_q(\n                            self.cta_tiler[0],\n                            curr_block_coord[0],\n                            seqlen_q,\n                        )\n                    )\n\n                if not continue_cond:\n                    batch_base = cuseqlen_q\n                    gate_vals = cute.make_rmem_tensor((4), cutlass.Float32)\n                    beta_vals = cute.make_rmem_tensor((4), cutlass.Float32)\n\n                    for i in cutlass.range(loop_count, unroll=1):\n                        # step1: read gate beta\n                        for it in cutlass.range_constexpr(4):\n                            curr_idx = i * 128 + it * 32 + lane_id\n                            if curr_idx < seqlen_q:\n                                if cutlass.const_expr(cum_seqlen_q is not None):\n                                    gate_vals[it] = gate[\n                                        batch_base + curr_idx, 0, (head_coord, 0)\n                                    ]\n                                    beta_vals[it] = beta[\n                                        batch_base + curr_idx, 0, (head_coord, 0)\n                                    ]\n                                else:\n                                    gate_vals[it] = gate[\n                                        curr_idx, 0, (head_coord, batch_coord)\n                                    ]\n                                    beta_vals[it] = beta[\n                                        curr_idx, 0, (head_coord, batch_coord)\n                                    ]\n                            else:\n                                gate_vals[it] = cutlass.Float32(0)\n                                beta_vals[it] = cutlass.Float32(0)\n                        # step2: write to smem\n                        sGate0 = sGate[None, None, 0]  # assume only one stage\n                        sBeta0 = sBeta[None, None, 0]\n\n                        gb_handle = gb_w0_producer.acquire_and_advance()\n\n                        for it in cutlass.range_constexpr(4):\n                            sGate0[it * 32 + lane_id] = gate_vals[it]\n                            sBeta0[it * 32 + lane_id] = beta_vals[it]\n\n                        # step3: notify cuda core wg\n                        gb_handle.commit()\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  Epilogue: Store Output\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx == self.epilogue_warp_id:\n            cute.arch.setmaxregister_decrease(self.num_regs_other)\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n\n                batch_coord = curr_block_coord[2][1]\n                continue_cond = False\n                cuseqlen_q = Int32(0)\n                seqlen_q = mQ_qdl.shape[0]\n\n                if cutlass.const_expr(cum_seqlen_q is not None):\n                    cuseqlen_q = cum_seqlen_q[batch_coord]\n                    seqlen_q = cum_seqlen_q[batch_coord + 1] - cuseqlen_q\n                    continue_cond = (\n                        not GdnStaticTileScheduler.check_valid_work_for_seqlen_q(\n                            self.cta_tiler[0],\n                            curr_block_coord[0],\n                            seqlen_q,\n                        )\n                    )\n\n                if not continue_cond:\n                    curr_block_coord_o = curr_block_coord\n                    mO_qdl_ = mO_qdl\n                    if cutlass.const_expr(cum_seqlen_q is not None):\n                        logical_offset_mO = (\n                            mO_qdl_.shape[0] - seqlen_q,\n                            0,\n                            (0, cuseqlen_q + seqlen_q),\n                        )\n                        mO_qdl_ = cute.domain_offset(logical_offset_mO, mO_qdl_)\n                        curr_block_coord_o = (\n                            curr_block_coord[0],\n                            curr_block_coord[1],\n                            (curr_block_coord[2][0], 0),\n                        )\n\n                    gO_mnl = cute.flat_divide(\n                        mO_qdl_, cute.select(self.mma_tiler, mode=[0, 1])\n                    )\n                    tOsO, tOgO_qdl = cute.nvgpu.cpasync.tma_partition(\n                        tma_atom_o_output,\n                        0,\n                        cute.make_layout(1),\n                        cute.group_modes(sO, 0, 2),\n                        cute.group_modes(gO_mnl, 0, 2),\n                    )\n                    tQgO = tOgO_qdl[None, None, 0, curr_block_coord_o[2]]\n                    w0_handle = epi_w0_producer.acquire_and_advance()\n                    w0_handle.commit()\n\n                    for i in cutlass.range(loop_count, unroll=1):\n                        w0_handle = epi_w0_producer.acquire_and_advance()\n                        cute.copy(tma_atom_o_output, tOsO[None, 0], tQgO[None, i])\n\n                        cute.arch.cp_async_bulk_commit_group()\n\n                        # Ensure O0 buffer is ready to be released\n                        cute.arch.cp_async_bulk_wait_group(0, read=True)\n\n                        w0_handle.commit()\n\n                    if cutlass.const_expr(tma_atom_state_output is not None):\n                        gStateOutput = cute.flat_divide(\n                            mStateOutput,\n                            cute.select(self.update_s_mma_tiler, mode=[0, 1]),\n                        )\n                        tSsS, tSgS_vkl = cute.nvgpu.cpasync.tma_partition(\n                            tma_atom_state_output,\n                            0,  # no multicast\n                            cute.make_layout(1),\n                            cute.group_modes(sStateOutput, 0, 2),\n                            cute.group_modes(gStateOutput, 0, 4),\n                        )\n                        tSgS = tSgS_vkl[None, curr_block_coord[2]]\n                        w0_epi_handle = w0_epi_consumer.wait_and_advance()\n                        cute.copy(\n                            tma_atom_state_output,\n                            tSsS[None, 0],  # only 1 stage\n                            tSgS[None],\n                        )\n                        cute.arch.cp_async_bulk_commit_group()\n                        cute.arch.cp_async_bulk_wait_group(0, read=True)\n                        w0_epi_handle.release()\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n\n                # The smem is reused, ensuring the State Output store is complete\n                if cutlass.const_expr(\n                    tma_atom_state_output is not None and self.is_persistent\n                ):\n                    cute.arch.barrier_arrive(\n                        barrier_id=self.epi_load_sync_bar_id,\n                        number_of_threads=self.threads_per_warp * 2,\n                    )\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  LOAD: tma load QKVS\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx == self.load_warp_id:\n            cute.arch.setmaxregister_decrease(self.num_regs_other)\n\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n                continue_cond = False\n                cuseqlen_q = Int32(0)\n                seqlen_q = mQ_qdl.shape[0]\n                batch_coord = curr_block_coord[2][1]\n\n                if cutlass.const_expr(cum_seqlen_q is not None):\n                    cuseqlen_q = cum_seqlen_q[batch_coord]\n                    seqlen_q = cum_seqlen_q[batch_coord + 1] - cuseqlen_q\n                    continue_cond = (\n                        not GdnStaticTileScheduler.check_valid_work_for_seqlen_q(\n                            self.cta_tiler[0],\n                            curr_block_coord[0],\n                            seqlen_q,\n                        )\n                    )\n\n                if not continue_cond:\n                    mQ_qdl_ = mQ_qdl\n                    mK_kdl_ = mK_kdl\n                    mV_dkl_ = mV_dkl\n                    curr_block_coord_q = curr_block_coord\n                    curr_block_coord_kv = curr_block_coord\n                    curr_block_coord_state = curr_block_coord\n\n                    if cutlass.const_expr(cum_seqlen_q is not None):\n                        logical_offset_mQ = (\n                            cuseqlen_q,\n                            0,\n                            (0, 0),\n                        )\n                        mQ_qdl_ = cute.domain_offset(logical_offset_mQ, mQ_qdl)\n                        curr_block_coord_q = (\n                            curr_block_coord[0],\n                            curr_block_coord[1],\n                            (curr_block_coord[2][0], Int32(0)),\n                        )\n                        logical_offset_mK = (\n                            cuseqlen_q,\n                            0,\n                            (0, 0),\n                        )\n                        logical_offset_mV = (\n                            0,\n                            cuseqlen_q,\n                            (0, 0),\n                        )\n                        mK_kdl_ = cute.domain_offset(logical_offset_mK, mK_kdl)\n                        mV_dkl_ = cute.domain_offset(logical_offset_mV, mV_dkl)\n                        curr_block_coord_kv = (\n                            curr_block_coord[0],\n                            curr_block_coord[1],\n                            (curr_block_coord[2][0], Int32(0)),\n                        )\n\n                    gQ_qdl = cute.flat_divide(\n                        mQ_qdl_, cute.select(self.qk_mma_tiler, mode=[0, 2])\n                    )\n                    tSgQ_qdl = qk_thr_mma.partition_A(gQ_qdl)\n\n                    tQsQ, tQgQ_qdl = cute.nvgpu.cpasync.tma_partition(\n                        tma_atom_q,\n                        0,  # no multicast\n                        cute.make_layout(1),\n                        cute.group_modes(sQK, 0, 3),\n                        cute.group_modes(tSgQ_qdl, 0, 3),\n                    )\n                    tQgQ = tQgQ_qdl[None, None, 0, curr_block_coord_q[2]]\n\n                    gK_kdl = cute.flat_divide(\n                        mK_kdl_, cute.select(self.qk_mma_tiler, mode=[1, 2])\n                    )\n                    tSgK_kdl = qk_thr_mma.partition_B(gK_kdl)\n                    tKsK, tKgK_kdl = cute.nvgpu.cpasync.tma_partition(\n                        tma_atom_k,\n                        0,  # no multicast\n                        cute.make_layout(1),\n                        cute.group_modes(sQK, 0, 3),\n                        cute.group_modes(tSgK_kdl, 0, 3),\n                    )\n                    tKgK = tKgK_kdl[None, None, 0, curr_block_coord_kv[2]]\n\n                    gV_kdl = cute.flat_divide(\n                        mV_dkl_, cute.select(self.tuw_mma_tiler, mode=[1, 2])\n                    )\n                    tSgV_kdl = tuw_thr_mma.partition_B(gV_kdl)\n                    tVsV, tVgV_kdl = cute.nvgpu.cpasync.tma_partition(\n                        tma_atom_v,\n                        0,  # no multicast\n                        cute.make_layout(1),\n                        cute.group_modes(sV, 0, 3),\n                        cute.group_modes(tSgV_kdl, 0, 3),\n                    )\n                    tVgV = tVgV_kdl[None, 0, None, curr_block_coord_kv[2]]\n\n                    if cutlass.const_expr(tma_atom_state_f32 is not None):\n                        gStateF32 = cute.flat_divide(\n                            mState_f32, cute.select(self.kst_mma_tiler, mode=[1, 2])\n                        )\n                        tKSgStateF32 = fake_state_thr_mma.partition_B(gStateF32)\n                        tSsSF32, tSgSF32_kdl = cute.nvgpu.cpasync.tma_partition(\n                            tma_atom_state_f32,\n                            0,  # no multicast\n                            cute.make_layout(1),\n                            cute.group_modes(sStateInputF32, 0, 3),\n                            cute.group_modes(tKSgStateF32, 0, 3),\n                        )\n                        tSgSF32 = tSgSF32_kdl[None, None, 0, curr_block_coord_state[2]]\n                        state_f32_handle0 = load_state_producer.acquire_and_advance()\n                        cute.copy(\n                            tma_atom_state_f32,\n                            tSgSF32[None, 0],\n                            tSsSF32[None, state_f32_handle0.index],\n                            tma_bar_ptr=state_f32_handle0.barrier,\n                        )\n\n                    for i in cutlass.range(loop_count, unroll=1):\n                        w0_coord = i\n                        k0_handle = load_qk_producer.acquire_and_advance()\n                        cute.copy(\n                            tma_atom_k,\n                            tKgK[None, w0_coord],\n                            tKsK[None, k0_handle.index],\n                            tma_bar_ptr=k0_handle.barrier,\n                        )\n\n                        q_handle = load_qk_producer.acquire_and_advance()\n                        cute.copy(\n                            tma_atom_q,\n                            tQgQ[None, w0_coord],\n                            tQsQ[None, q_handle.index],\n                            tma_bar_ptr=q_handle.barrier,\n                        )\n\n                        v_handle0 = load_v_producer.acquire_and_advance()\n                        cute.copy(\n                            tma_atom_v,\n                            tVgV[None, w0_coord],\n                            tVsV[None, v_handle0.index],\n                            tma_bar_ptr=v_handle0.barrier,\n                        )\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n\n                if cutlass.const_expr(\n                    tma_atom_state_output is not None and self.is_persistent\n                ):\n                    cute.arch.barrier(\n                        barrier_id=self.epi_load_sync_bar_id,\n                        number_of_threads=self.threads_per_warp * 2,\n                    )\n            # dealloc tmem buffer\n            cute.arch.relinquish_tmem_alloc_permit()\n            cute.arch.mbarrier_wait(tmem_dealloc_mbar_ptr, 0)\n            tmem_alloc_cols = Int32(self.tmem_alloc_cols)\n            #  Retrieving tmem ptr and make acc\n            tmem_ptr = cute.arch.retrieve_tmem_ptr(\n                cutlass.Float32,\n                alignment=16,\n                ptr_to_buffer_holding_addr=storage.tmem_holding_buf,\n            )\n            cute.arch.dealloc_tmem(tmem_ptr, tmem_alloc_cols)\n\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  MMA: mma warp\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx == self.mma_warp_id:\n            cute.arch.setmaxregister_decrease(self.num_regs_mma)\n\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n\n            tSrDC_ivt_l1_fake = invert_sub_thr_mma_ts_l1.make_fragment_A(\n                invert_sub_smem_layout_staged_ts_l1_a.outer.shape\n            )\n            tSrDC_ivt_l1 = cute.make_tensor(\n                cute.recast_ptr(\n                    tmem_ptr,\n                    dtype=tSrDC_ivt_l1_fake.element_type,\n                )\n                + self.tmem_ivt_ts_l1_input,\n                tSrDC_ivt_l1_fake.layout,\n            )\n            tSrA_ivt_l1 = invert_sub_thr_mma_ts_l1.make_fragment_B(sInvertSubTSL1B)\n\n            tOrP = o_intra_thr_mma_new.make_fragment_A(\n                o_intra_smem_layout_staged_a_new.outer\n            )\n            tOrP0 = cute.make_tensor(\n                cute.recast_ptr(\n                    tmem_ptr,\n                    dtype=tOrP.element_type,\n                )\n                + self.tmem_gate_qk * 2,\n                tOrP.layout,\n            )\n\n            tQSA = o_intra_thr_mma_new.make_fragment_A(qs_smem_layout_staged_a.outer)\n            tQSA0 = cute.make_tensor(\n                cute.recast_ptr(\n                    tmem_ptr,\n                    dtype=tQSA.element_type,\n                )\n                + self.tmem_gate_q * 2,\n                tQSA.layout,\n            )\n\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n                continue_cond = False\n\n                if not continue_cond:\n                    for _i in cutlass.range(loop_count, unroll=1):\n                        k_handle0 = load_qk_consumer.wait_and_advance()\n                        qk_handle0 = mma_qk_producer0.acquire_and_advance()\n\n                        kkt_tiled_mma = self.exec_mma(\n                            kkt_tiled_mma,\n                            tKKTtKKT,\n                            tArK,\n                            tArKT,\n                            k_handle0.index,\n                            k_handle0.index,\n                        )\n\n                        qk_handle0.commit()\n\n                        q_handle = load_qk_consumer.wait_and_advance()\n\n                        qk_handle1 = mma_qk_producer0.acquire_and_advance()\n\n                        qk_tiled_mma = self.exec_mma(\n                            qk_tiled_mma,\n                            tQKtQK,\n                            tSrQ,\n                            tSrK,\n                            q_handle.index,\n                            k_handle0.index,\n                        )\n\n                        qk_handle1.commit()\n\n                        cs_handle = mma_cudacore_producer0.acquire_and_advance()\n                        cute.arch.barrier(\n                            barrier_id=self.cudacore_mma_sync_bar_id,\n                            number_of_threads=self.threads_per_warp * 5,\n                        )\n\n                        kst_tiled_mma = self.exec_mma(\n                            kst_tiled_mma,\n                            tKStKS,\n                            tKSrK_0,\n                            tKSrST,\n                            0,\n                            0,\n                        )\n\n                        cs_handle.commit()\n\n                        cs_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        invert_sub_tiled_mma_ss_l0 = self.exec_mma(\n                            invert_sub_tiled_mma_ss_l0,\n                            tItSSL0,\n                            tSrD,\n                            tSrC,\n                            0,\n                            0,\n                        )\n\n                        cs_handle.commit()\n\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        invert_sub_tiled_mma_ts_l0 = self.exec_mma(\n                            invert_sub_tiled_mma_ts_l0,\n                            tItTSL0,\n                            tInrDCL0A,\n                            tSrDCL0B,\n                            0,\n                            0,\n                        )\n\n                        c0_handle.commit()\n\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        invert_sub_tiled_mma_ss_l1 = self.exec_mma(\n                            invert_sub_tiled_mma_ss_l1,\n                            tStO_ivt_l1_ss0,\n                            tSrD_ivt_l1,\n                            tSrC_ivt_l1,\n                            0,\n                            0,\n                        )\n\n                        c0_handle.commit()\n\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        k_handle0.release()\n\n                        invert_sub_tiled_mma_ts_l1 = self.exec_mma(\n                            invert_sub_tiled_mma_ts_l1,\n                            tOtTSL1,\n                            tSrDC_ivt_l1,\n                            tSrA_ivt_l1,\n                            0,\n                            0,\n                        )\n\n                        c0_handle.commit()\n\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        tuw_tiled_mma = self.exec_mma(\n                            tuw_tiled_mma,\n                            tVtTUW,\n                            tTUWrA,\n                            tTUWrB,\n                            0,\n                            0,\n                        )\n\n                        c0_handle.commit()\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        q_handle.release()\n\n                        tCtAcc_o_intra_acc_shape_fake = o_intra_thr_mma.make_fragment_C(\n                            o_intra_acc_shape\n                        )\n                        tStO_o_intra0 = cute.make_tensor(\n                            tmem_ptr + self.tmem_o_intra_output,\n                            tCtAcc_o_intra_acc_shape_fake.layout,\n                        )\n\n                        o_intra_tiled_ts_mma_new = self.exec_mma(\n                            o_intra_tiled_ts_mma_new,\n                            tStO_o_intra0,\n                            tOrP0,\n                            tOIntrarB,\n                            0,\n                            0,\n                        )\n\n                        qs_tiled_mma = self.exec_mma(\n                            qs_tiled_mma,\n                            tOintertQS,\n                            tQSA0,\n                            tQSB,\n                            0,\n                            0,\n                            True,\n                        )\n\n                        c0_handle.commit()\n                        c0_handle = mma_cudacore_producer0.acquire_and_advance()\n\n                        update_s_tiled_mma = self.exec_mma(\n                            update_s_tiled_mma,\n                            tStUpdate,\n                            tUpdateA,\n                            tUpdateB,\n                            0,\n                            0,\n                            True,\n                        )\n\n                        c0_handle.commit()\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n                # End of persistent scheduler loop\n        # ///////////////////////////////////////////////////////////////////////////////\n        #  Mainloop: mainloop warp group\n        # ///////////////////////////////////////////////////////////////////////////////\n        if warp_idx < 4:\n            cute.arch.setmaxregister_increase(self.num_regs_cudacore)\n\n            tile_sched = create_gdn_static_tile_scheduler(\n                tile_sched_params, cute.arch.block_idx(), cute.arch.grid_dim()\n            )\n            work_tile = tile_sched.initial_work_tile_info()\n\n            while work_tile.is_valid_tile:\n                curr_block_coord = work_tile.tile_idx\n                batch_coord = curr_block_coord[2][1]\n                continue_cond = False\n                if not continue_cond:\n                    gO_mnl = cute.flat_divide(\n                        O, cute.select(self.mma_tiler, mode=[0, 1])\n                    )\n                    # Use input state\n                    if cutlass.const_expr(tma_atom_state_f32 is not None):\n                        load_state_consumer.wait_and_advance()\n                        self.init_state_from_smem(\n                            kst_thr_mma,\n                            tStateF32,\n                            sStateInputF32,\n                        )\n                        load_state_consumer.release()\n                    else:\n                        self.init_state_zeros(\n                            kst_thr_mma,\n                            tStateF32,\n                        )\n\n                    # Arguments\n                    atom_args = (\n                        kkt_thr_mma,\n                        kst_thr_mma,\n                        qk_thr_mma,\n                        qs_thr_mma,\n                    )\n                    tensor_args = (\n                        sGate,\n                        sBeta,\n                        sGateCumsum,\n                        sStateInput,\n                        sIvt,\n                        sQ,\n                        sK,\n                        sV,\n                        sO,\n                        sInvertSubReg,\n                        sInvertSubSSL0A,\n                        sInvertSubSSL0B,\n                        sInvertSubSSL1B,\n                        sInvertSubTSL0B,\n                        sInvertSubSSL1A,\n                        sInvertSubTSL1B,\n                        sTuwAStore,\n                        sTuwA,\n                        sOIntraB,\n                        sUpdateB,\n                        tGamma,\n                        tKKTtKKT,\n                        tQKtQK,\n                        tQKMtQKM,\n                        tKtK,\n                        tKStKS,\n                        tItTSL0,\n                        tInrDCL0A,\n                        tOtTSL1,\n                        tVtTUW,\n                        tOintertQS,\n                        tItSSL0,\n                        tStateF32,\n                        tQgate,\n                    )\n                    pipeline_args = (\n                        gb_w0_consumer,\n                        epi_w0_consumer,\n                        mma_qk_consumer0,\n                        mma_cudacore_consumer0,\n                        load_v_consumer,\n                    )\n\n                    # Corner case\n                    tail_count = mO_qdl.shape[0] % self.cta_tiler[0]\n\n                    if tail_count == 0:\n                        value_args = (\n                            scale,\n                            loop_count,\n                            0,\n                        )\n                        (\n                            gb_w0_consumer,\n                            epi_w0_consumer,\n                            mma_qk_consumer0,\n                            mma_cudacore_consumer0,\n                            load_v_consumer,\n                        ) = self.main_loop(\n                            value_args,\n                            atom_args,\n                            tensor_args,\n                            pipeline_args,\n                        )\n                    else:\n                        value_args = (\n                            scale,\n                            loop_count - 1,\n                            0,\n                        )\n                        (\n                            gb_w0_consumer,\n                            epi_w0_consumer,\n                            mma_qk_consumer0,\n                            mma_cudacore_consumer0,\n                            load_v_consumer,\n                        ) = self.main_loop(\n                            value_args,\n                            atom_args,\n                            tensor_args,\n                            pipeline_args,\n                        )\n                        pipeline_args = (\n                            gb_w0_consumer,\n                            epi_w0_consumer,\n                            mma_qk_consumer0,\n                            mma_cudacore_consumer0,\n                            load_v_consumer,\n                        )\n                        value_args = (\n                            scale,\n                            1,\n                            loop_count - 1,\n                        )\n                        (\n                            gb_w0_consumer,\n                            epi_w0_consumer,\n                            mma_qk_consumer0,\n                            mma_cudacore_consumer0,\n                            load_v_consumer,\n                        ) = self.main_loop(\n                            value_args,\n                            atom_args,\n                            tensor_args,\n                            pipeline_args,\n                            True,\n                            tail_count=tail_count,\n                        )\n\n                    # Output state\n                    if cutlass.const_expr(tma_atom_state_output is not None):\n                        w0_epi_handle = w0_epi_producer.acquire_and_advance()\n                        self.store_state_to_smem(\n                            tStUpdate, sStateOutput, update_s_thr_mma\n                        )\n                        w0_epi_handle.commit()\n\n                    w0_handle = epi_w0_consumer.wait_and_advance()\n                    w0_handle.release()\n\n                tile_sched.advance_to_next_work()\n                work_tile = tile_sched.get_current_work()\n\n            cute.arch.mbarrier_arrive(tmem_dealloc_mbar_ptr)\n\n    @cute.jit\n    def main_loop(\n        self,\n        value_args: tuple,\n        atom_args: tuple,\n        tensor_args: tuple,\n        pipeline_args: tuple,\n        need_mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ) -> Tuple[\n        pipeline.PipelineConsumer,\n        pipeline.PipelineConsumer,\n        pipeline.PipelineConsumer,\n        pipeline.PipelineConsumer,\n        pipeline.PipelineConsumer,\n    ]:\n        \"\"\"Per-chunk mainloop executed by cudacore warps (0-3).\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        (\n            scale,\n            loop_count,\n            loop_base,\n        ) = value_args\n\n        (\n            kkt_thr_mma,\n            kst_thr_mma,\n            qk_thr_mma,\n            qs_thr_mma,\n        ) = atom_args\n\n        (\n            sGate,\n            sBeta,\n            sGateCumsum,\n            sStateInput,\n            sIvt,\n            sQ,\n            sK,\n            sV,\n            sO,\n            sInvertSubReg,\n            sInvertSubSSL0A,\n            sInvertSubSSL0B,\n            sInvertSubSSL1B,\n            sInvertSubTSL0B,\n            sInvertSubSSL1A,\n            sInvertSubTSL1B,\n            sTuwAStore,\n            sTuwA,\n            sOIntraB,\n            sUpdateB,\n            tGamma,\n            tKKTtKKT,\n            tQKtQK,\n            tQKMtQKM,\n            tKtK,\n            tKStKS,\n            tItTSL0,\n            tInrDCL0A,\n            tOtTSL1,\n            tVtTUW,\n            tOintertQS,\n            tItSSL0,\n            tStateF32,\n            tQgate,\n        ) = tensor_args\n\n        (\n            gb_w0_consumer,\n            epi_w0_consumer,\n            mma_qk_consumer0,\n            mma_cudacore_consumer0,\n            load_v_consumer,\n        ) = pipeline_args\n\n        for _i in cutlass.range(loop_base, loop_base + loop_count, unroll=1):\n            gb_handle = gb_w0_consumer.wait_and_advance()\n            sGate0 = sGate[None, None, gb_handle.index]\n            sBeta0 = sBeta[None, None, gb_handle.index]\n            tval = self.chunk_local_cumsum(sGate0, sGateCumsum, self.wg_sync_bar_id)\n            beta_val = sBeta0[tidx]\n            gb_handle.release()\n\n            self.compute_gamma_tmem(\n                tval,\n                sGateCumsum,\n                kkt_thr_mma,\n                tGamma,\n                self.wg_sync_bar_id,\n                need_mask,\n                tail_count,\n            )\n            qk_handle0 = mma_qk_consumer0.wait_and_advance()\n\n            self.apply_gamma_beta(\n                kkt_thr_mma,\n                sIvt,\n                tKKTtKKT,\n                beta_val,\n                tGamma,\n            )\n\n            gate_tail = (\n                sGateCumsum[tail_count - 1]\n                if cutlass.const_expr(need_mask)\n                else sGateCumsum[127]\n            )\n            w0_handle = epi_w0_consumer.wait_and_advance()\n            self.load_state_apply_gate(\n                kst_thr_mma,\n                tStateF32,\n                sStateInput,\n                gate_tail,\n            )\n            cute.arch.fence_proxy(\n                cute.arch.ProxyKind.async_shared,\n                space=cute.arch.SharedSpace.shared_cta,\n            )\n\n            qk_handle1 = mma_qk_consumer0.wait_and_advance()\n            self.load_qk_epi(\n                qk_thr_mma, tQKtQK, tQKMtQKM, tGamma, need_mask, tail_count\n            )\n\n            cute.arch.barrier_arrive(\n                barrier_id=self.cudacore_mma_sync_bar_id,\n                number_of_threads=self.threads_per_warp * 5,\n            )\n\n            reverse_result = cute.make_rmem_tensor((32, 1), self.acc_dtype)\n\n            self.reverse_smem_sub(reverse_result, sIvt)\n\n            self.store_ivt_smem_l0_ss_a(\n                reverse_result,\n                sInvertSubReg,\n                sInvertSubSSL0A,\n            )\n\n            self.store_ivt_smem_l0_ss_b(\n                kkt_thr_mma,\n                tKKTtKKT,\n                sInvertSubSSL0B,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            c0_handle.release()\n            v_handle0 = load_v_consumer.wait_and_advance()\n\n            tval_exp = cute.math.exp(tval)\n            self.get_uw_b(\n                kst_thr_mma, tKStKS, tval_exp, beta_val, sV, need_mask, tail_count\n            )\n            self.store_ivt_p1(\n                sInvertSubReg,\n                sInvertSubTSL0B,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            self.load_ivt_ss_l0(tItSSL0, tInrDCL0A)  # debug\n            c0_handle.release()\n            self.store_ivt_smem_l1_ss_b(\n                kkt_thr_mma,\n                tKKTtKKT,\n                sInvertSubSSL1B,\n            )\n\n            self.store_ivt_p2(\n                sInvertSubReg,\n                sInvertSubSSL1A,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n\n            self.load_ivt_ts_l0(\n                tItTSL0,\n                sInvertSubSSL1A,\n                sInvertSubTSL1B,\n            )\n\n            c0_handle.release()\n\n            self.store_k_epi(kkt_thr_mma, sK, tKtK, need_mask, tail_count)\n            self.store_ivt_p3(\n                sInvertSubReg,\n                sInvertSubTSL1B,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            c0_handle.release()\n            self.save_tmem(tItTSL0, sTuwAStore)\n            self.store_ivt_ad(sInvertSubReg, sTuwA)\n            self.store_ivt_c(sTuwAStore)\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            self.load_ivt_result(tOtTSL1, sTuwAStore)\n            c0_handle.release()\n\n            self.load_q_epi(qk_thr_mma, sQ, tQgate, tval_exp, need_mask, tail_count)\n            cute.arch.fence_proxy(\n                cute.arch.ProxyKind.async_shared,\n                space=cute.arch.SharedSpace.shared_cta,\n            )\n\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            v_handle0.release()\n            self.load_v(tVtTUW, sOIntraB)\n            c0_handle.release()\n            self.load_k(tKtK, sUpdateB, gate_tail, tval)\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            qk_handle0.release()\n            c0_handle.release()\n            self.store_o_smem(tOintertQS, sO, qs_thr_mma, scale)\n\n            w0_handle.release()\n            qk_handle1.release()\n            c0_handle = mma_cudacore_consumer0.wait_and_advance()\n            c0_handle.release()\n\n        return (\n            gb_w0_consumer,\n            epi_w0_consumer,\n            mma_qk_consumer0,\n            mma_cudacore_consumer0,\n            load_v_consumer,\n        )\n\n    @cute.jit\n    def exec_mma(\n        self,\n        tiled_mma,\n        tCtAcc,\n        tCrA,\n        tCrB,\n        a_consumer_index,\n        b_consumer_index,\n        setAcc: bool = False,\n    ):\n        \"\"\"Issue a tcgen05 GEMM.\"\"\"\n        for kphase_idx in cutlass.range(cute.size(tCrB, mode=[2]), unroll_all=True):\n            # set accu = 1\n            tiled_mma.set(\n                tcgen05.Field.ACCUMULATE,\n                cutlass.Boolean(kphase_idx != 0 or setAcc),\n            )\n            cute.gemm(\n                tiled_mma,\n                tCtAcc,\n                tCrA[None, None, kphase_idx, a_consumer_index],\n                tCrB[None, None, kphase_idx, b_consumer_index],\n                tCtAcc,\n            )\n        return tiled_mma\n\n    @cute.jit\n    def get_uw_b(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        gate_val: cutlass.Float32,\n        beta_val: cutlass.Float32,\n        sV: cute.Tensor,\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Compute V_new = beta*V - beta*gamma*(K@S^T) in-place in smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 64\n        corr_tile_size_f32 = corr_tile_size // 2\n\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        frg_tile = 8\n        sV_frg = cute.logical_divide(sV, cute.make_layout(frg_tile))\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n        tTMEM_LOADrS_frag = cute.logical_divide(\n            tTMEM_LOADrS, cute.make_layout(frg_tile)\n        )\n\n        if cutlass.const_expr(mask):\n            if thread_idx >= tail_count:\n                beta_val = self.g_beta_dtype(0)\n\n        combined_factor = gate_val * beta_val\n\n        each_iter = corr_tile_size // frg_tile\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n\n            # Load V from smem\n            temp_regs = cute.make_rmem_tensor(tTMEM_LOADrS_frag.shape, self.acc_dtype)\n            for it in cutlass.range_constexpr(each_iter):\n                for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                    # mul2\n                    (\n                        temp_regs[inner_idx + 0, it],\n                        temp_regs[inner_idx + 1, it],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (\n                            tTMEM_LOADrS_frag[inner_idx + 0, it],\n                            tTMEM_LOADrS_frag[inner_idx + 1, it],\n                        ),\n                        (-combined_factor, -combined_factor),\n                    )\n\n                    # fma2\n                    (\n                        temp_regs[inner_idx + 0, it],\n                        temp_regs[inner_idx + 1, it],\n                    ) = cute.arch.fma_packed_f32x2(\n                        (\n                            beta_val,\n                            beta_val,\n                        ),\n                        (\n                            cutlass.Float32(\n                                sV_frg[inner_idx + 0, (i * each_iter + it, thread_idx)]\n                            ),\n                            cutlass.Float32(\n                                sV_frg[inner_idx + 1, (i * each_iter + it, thread_idx)]\n                            ),\n                        ),\n                        (\n                            temp_regs[inner_idx + 0, it],\n                            temp_regs[inner_idx + 1, it],\n                        ),\n                    )\n                sV_frg[None, (i * each_iter + it, thread_idx)].store(\n                    temp_regs[None, it].load().to(self.i_dtype)\n                )\n\n    @cute.jit\n    def store_state_to_smem(\n        self,\n        tO: cute.Tensor,\n        sO: cute.Tensor,\n        thr_mma: cute.ThrMma,\n    ):\n        \"\"\"Copy final state from TMEM to smem for TMA store to global.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tOcO = thr_mma.partition_C(tO)\n        tOsO = thr_mma.partition_C(sO)\n\n        corr_tile_size = 32  # must >= 8\n        tOsO_sub = cute.make_tensor(\n            cute.recast_ptr(tOsO.iterator, dtype=self.state_dtype),\n            cute.shape(tOsO)[0],\n        )\n        tOsO_tile = cute.logical_divide(\n            tOsO_sub, (None, (None, 32 // (128 // corr_tile_size)))\n        )\n\n        tIn_i_layout = cute.composition(\n            tO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        sOut_i_layout = cute.composition(\n            tOsO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tIn_i = cute.make_tensor(tO.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(tOcO.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        smem_copy_atom = sm100_utils.get_smem_store_op(\n            self.s_output, self.state_dtype, self.acc_dtype, tiled_tmem_load\n        )\n        tiled_smem_store = cute.make_tiled_copy_D(smem_copy_atom, tiled_tmem_load)\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            sOut_i_sub = cute.make_tensor(\n                tOsO_tile[None, (None, (None, i))].iterator, sOut_i_layout\n            )\n            tTMEM_STOREsO_i = thr_tmem_load.partition_D(sOut_i_sub)\n            cute.copy(tiled_smem_store, tTMEM_LOADrS, tTMEM_STOREsO_i)\n\n        # fence view async shared\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_o_smem(\n        self,\n        tO: cute.Tensor,\n        sO: cute.Tensor,\n        thr_mma: cute.ThrMma,\n        scale: cutlass.Float32,\n    ):\n        \"\"\"Scale and convert O from TMEM (f32) to smem (f16/bf16) for TMA store.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tOcO = thr_mma.partition_C(tO)\n        tOsO = thr_mma.partition_C(sO)\n\n        corr_tile_size = 128  # must >= 8\n\n        # ((128,(8,16)),1,1,(1,1))\n        tOsO_sub = cute.make_tensor(\n            cute.recast_ptr(tOsO.iterator, dtype=self.i_dtype),\n            cute.shape(tOsO)[0],\n        )\n        tOsO_tile = cute.logical_divide(\n            tOsO_sub, (None, (None, 16 // (128 // corr_tile_size)))\n        )\n\n        tIn_i_layout = cute.composition(\n            tO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        sOut_i_layout = cute.composition(\n            tOsO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tIn_i = cute.make_tensor(tO.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(tOcO.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_STORErS_x4_e = cute.make_tensor(\n            cute.recast_ptr(tTMEM_LOADrS.iterator, dtype=self.i_dtype),\n            tTMEM_LOADrS.layout,\n        )\n\n        smem_copy_atom = sm100_utils.get_smem_store_op(\n            self.o_layout, self.i_dtype, self.acc_dtype, tiled_tmem_load\n        )\n        tiled_smem_store = cute.make_tiled_copy_D(smem_copy_atom, tiled_tmem_load)\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n\n            frg_cnt = 4  # must 4\n            frg_tile = cute.size(tTMEM_LOADrS) // frg_cnt\n            tTMEM_LOADrS_frg = cute.logical_divide(\n                tTMEM_LOADrS, cute.make_layout(frg_tile)\n            )\n            tTMEM_STORErS_x4_e_frg = cute.logical_divide(\n                tTMEM_STORErS_x4_e, cute.make_layout(frg_tile)\n            )\n\n            temp_regs = cute.make_rmem_tensor(tTMEM_LOADrS_frg.shape, self.acc_dtype)\n            for j in cutlass.range_constexpr(frg_cnt):\n                for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                    # mul2\n                    (\n                        temp_regs[inner_idx + 0, j],\n                        temp_regs[inner_idx + 1, j],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (\n                            tTMEM_LOADrS_frg[inner_idx + 0, j],\n                            tTMEM_LOADrS_frg[inner_idx + 1, j],\n                        ),\n                        (scale, scale),\n                    )\n                tTMEM_STORErS_x4_e_frg[None, j].store(\n                    temp_regs[None, j].load().to(self.i_dtype)\n                )\n\n            # store\n            sOut_i_sub = cute.make_tensor(\n                tOsO_tile[None, (None, (None, i))].iterator, sOut_i_layout\n            )\n            tTMEM_STOREsO_i = thr_tmem_load.partition_D(sOut_i_sub)\n            cute.copy(tiled_smem_store, tTMEM_STORErS_x4_e, tTMEM_STOREsO_i)\n\n        # fence view async shared\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def load_k(\n        self,\n        tIn: cute.Tensor,\n        sUpdateB: cute.Tensor,\n        gate: cutlass.Float32,\n        val: cutlass.Float32,\n    ):\n        \"\"\"Load K from TMEM, apply per-token gate decay.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        gate_val = cute.math.exp((gate - val))\n\n        k = self.read_tmem_128(tIn)\n\n        k_f16 = cute.make_tensor(\n            cute.recast_ptr(k.iterator, dtype=self.i_dtype),\n            cute.make_layout(128),\n        )\n        k_f16_frag = cute.logical_divide(k_f16, cute.make_layout(8))\n\n        for bid in cutlass.range_constexpr(0, 2):\n            for col in cutlass.range_constexpr(0, 8):\n                load_row = thread_idx\n\n                store_row = load_row\n                store_col = bid * 8 + col\n\n                store_row_bid = store_row // 16\n                store_row_offset = store_row % 16\n                sUpdateB[\n                    ((None, store_col), store_row_offset), 0, store_row_bid, 0\n                ].store(\n                    (k_f16_frag[None, store_col].load() * gate_val).to(self.i_dtype)\n                )\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def init_state_zeros(\n        self,\n        thr_mma: cute.ThrMma,\n        tOutF32: cute.Tensor,\n    ):\n        \"\"\"Zero-initialize the recurrent state in TMEM (no initial_state provided).\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n        corr_tile_size = 128\n\n        # Apply gate State\n        cInOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tInOut_i_layout = cute.composition(\n            tOutF32.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tInOut_i = cute.make_tensor(tOutF32.iterator, tInOut_i_layout)\n        cInOut_i = cute.make_tensor(tOcO.iterator, cInOut_i_layout)\n\n        tmem_store_atom_f32 = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store_f32 = tcgen05.make_tmem_copy(tmem_store_atom_f32, tInOut_i)\n        thr_tmem_store_f32 = tiled_tmem_store_f32.get_slice(thread_idx)\n\n        tTMEM_STOREtInOut = thr_tmem_store_f32.partition_D(tInOut_i)\n        tTMEM_STOREcInOut = thr_tmem_store_f32.partition_S(cInOut_i)\n        tTMEM_STORErInOut = cute.make_rmem_tensor(\n            tTMEM_STOREcInOut.shape, self.acc_dtype\n        )\n\n        frg_tile = 4\n        zeros = cute.zeros_like(cute.make_layout(frg_tile), self.acc_dtype)\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtInOut_i = cute.make_tensor(\n                tTMEM_STOREtInOut.iterator + i * corr_tile_size,\n                tTMEM_STOREtInOut.layout,\n            )\n\n            tTMEM_STORErInOut_frg = cute.logical_divide(\n                tTMEM_STORErInOut, ((frg_tile, None), None)\n            )\n\n            each_iter = corr_tile_size // frg_tile\n            for j in cutlass.range_constexpr(each_iter):\n                tTMEM_STORErInOut_frg[((None, j), 0), 0, 0].store(zeros)\n\n            # store\n            cute.copy(tiled_tmem_store_f32, tTMEM_STORErInOut, tTMEM_STOREtInOut_i)\n            cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def init_state_from_smem(\n        self,\n        thr_mma: cute.ThrMma,\n        tOutF32: cute.Tensor,\n        sStateInputF32: cute.Tensor,\n    ):\n        \"\"\"Load initial_state from smem (f32) into TMEM.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 128\n        cInOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tInOut_i_layout = cute.composition(\n            tOutF32.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tInOut_i = cute.make_tensor(tOutF32.iterator, tInOut_i_layout)\n        cInOut_i = cute.make_tensor(tOcO.iterator, cInOut_i_layout)\n\n        tmem_store_atom_f32 = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store_f32 = tcgen05.make_tmem_copy(tmem_store_atom_f32, tInOut_i)\n        thr_tmem_store_f32 = tiled_tmem_store_f32.get_slice(thread_idx)\n\n        tTMEM_STOREtInOut = thr_tmem_store_f32.partition_D(tInOut_i)\n        tTMEM_STOREcInOut = thr_tmem_store_f32.partition_S(cInOut_i)\n        tTMEM_STORErInOut = cute.make_rmem_tensor(\n            tTMEM_STOREcInOut.shape, self.acc_dtype\n        )\n\n        frg_tile = 4  # must 4\n        sStateInputF32_frag = cute.logical_divide(\n            sStateInputF32, (((None, frg_tile), None))\n        )\n        tTMEM_STORErInOut_frg = cute.logical_divide(\n            tTMEM_STORErInOut, ((frg_tile, None), None)\n        )\n        each_iter = corr_tile_size // frg_tile\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtInOut_i = cute.make_tensor(\n                tTMEM_STOREtInOut.iterator + i * corr_tile_size,\n                tTMEM_STOREtInOut.layout,\n            )\n\n            # Load from smem\n            idx_offset = i * corr_tile_size\n            for j in cutlass.range_constexpr(each_iter):\n                idx = idx_offset + j * frg_tile\n                bid = idx // 32\n                bid_inner = idx % 32 // 8\n                inner_idx = idx % 8 // 4\n                s_vec = sStateInputF32_frag[\n                    (thread_idx, (None, inner_idx)), 0, (bid_inner, bid), 0\n                ].load()\n                tTMEM_STORErInOut_frg[((None, j), 0), 0, 0].store(s_vec)\n\n            # store\n            cute.copy(tiled_tmem_store_f32, tTMEM_STORErInOut, tTMEM_STOREtInOut_i)\n            cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def load_state_apply_gate(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        sStateInput: cute.Tensor,\n        gate: cutlass.Float32,\n    ):\n        \"\"\"Apply chunk-level gate decay to state in TMEM, and copy state to smem (f16) for KST GEMM.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 16\n        # corr_tile_size_f32 = corr_tile_size // 2\n\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        # Apply gate State\n        # cInOut_i_layout = cute.composition(tOcO.layout, cute.make_layout((128, corr_tile_size)))\n        tInOut_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        # fp16 state\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tInOut_i = cute.make_tensor(tIn.iterator, tInOut_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tmem_store_atom_f32 = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        tiled_tmem_store_f32 = tcgen05.make_tmem_copy(tmem_store_atom_f32, tInOut_i)\n\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n        thr_tmem_store_f32 = tiled_tmem_store_f32.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_STOREtInOut = thr_tmem_store_f32.partition_D(tInOut_i)\n        tTMEM_STORErInOut = cute.make_tensor(\n            cute.recast_ptr(tTMEM_LOADrS.iterator, dtype=self.acc_dtype),\n            tTMEM_LOADrS.layout,\n        )\n\n        gate_val = cute.math.exp(gate)\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            tTMEM_STOREtInOut_i = cute.make_tensor(\n                tTMEM_STOREtInOut.iterator + i * corr_tile_size,\n                tTMEM_STOREtInOut.layout,\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n\n            frg_tile = 16  # must <= 16\n            tTMEM_LOADrS_frg = cute.logical_divide(\n                tTMEM_LOADrS, ((frg_tile, None), None)\n            )\n            tTMEM_STORErInOut_frg = cute.logical_divide(\n                tTMEM_STORErInOut, ((frg_tile, None), None)\n            )\n            sStateInput_frag = cute.logical_divide(\n                sStateInput, (((None, frg_tile), None))\n            )\n\n            each_iter = corr_tile_size // frg_tile\n            idx_offset = i * corr_tile_size\n            for j in cutlass.range_constexpr(each_iter):\n                s_vec = tTMEM_LOADrS_frg[((None, j), 0), 0, 0].load()\n                s_vec_f16 = s_vec.to(self.q_dtype)\n                idx = idx_offset + j * frg_tile\n                bid = idx // 64\n                bid_inner = idx % 64 // 16\n                inner_idx = idx % 16 // frg_tile\n                sStateInput_frag[\n                    (thread_idx, (None, inner_idx)), 0, (bid_inner, bid), 0\n                ].store(s_vec_f16)\n                # tTMEM_STORErInOut_frg[((None, j), 0), 0, 0].store(s_vec * gate_val)\n\n                for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                    (\n                        tTMEM_STORErInOut_frg[((inner_idx + 0, j), 0), 0, 0],\n                        tTMEM_STORErInOut_frg[((inner_idx + 1, j), 0), 0, 0],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (s_vec[inner_idx + 0], s_vec[inner_idx + 1]),\n                        (\n                            gate_val,\n                            gate_val,\n                        ),\n                    )\n            cute.copy(tiled_tmem_store_f32, tTMEM_STORErInOut, tTMEM_STOREtInOut_i)\n            cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def load_qk_epi(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        tOut: cute.Tensor,\n        tGamma: cute.Tensor,  # causal gate mask\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Apply gamma mask to QK^T.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 32\n        corr_tile_size_f32 = corr_tile_size // 2\n\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        cOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        tGamma_i = cute.make_tensor(tGamma.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        # Load Gamma\n        tiled_tmem_load_gamma = tcgen05.make_tmem_copy(tmem_load_atom, tGamma_i)\n        thr_tmem_load_gamma = tiled_tmem_load_gamma.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_LOADtG = thr_tmem_load_gamma.partition_S(tGamma_i)\n        tTMEM_LOADrG = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_STORErS_x4 = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n        tTMEM_STORErS_x4_e = cute.make_tensor(\n            cute.recast_ptr(tTMEM_STORErS_x4.iterator, dtype=self.i_dtype),\n            tTMEM_LOADrS.layout,\n        )\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size_f32, tTMEM_STOREtO.layout\n            )\n            tTMEM_LOADtG_i = cute.make_tensor(\n                tTMEM_LOADtG.iterator + i * corr_tile_size, tTMEM_LOADrG.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.copy(tiled_tmem_load_gamma, tTMEM_LOADtG_i, tTMEM_LOADrG)\n\n            frg_tile = 2\n            tTMEM_LOADrS_frg = cute.logical_divide(\n                tTMEM_LOADrS, ((frg_tile, None), None)\n            )\n            tTMEM_LOADrG_frg = cute.logical_divide(\n                tTMEM_LOADrG, ((frg_tile, None), None)\n            )\n            tTMEM_STORErS_x4_e_frg = cute.logical_divide(\n                tTMEM_STORErS_x4_e, cute.make_layout(frg_tile)\n            )\n\n            each_iter = corr_tile_size // frg_tile\n            for j in cutlass.range_constexpr(each_iter):\n                for it in cutlass.range_constexpr(0, frg_tile, 2):\n                    (\n                        tTMEM_LOADrS_frg[((it + 0, j), 0), 0, 0],\n                        tTMEM_LOADrS_frg[((it + 1, j), 0), 0, 0],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (\n                            tTMEM_LOADrS_frg[((it + 0, j), 0), 0, 0],\n                            tTMEM_LOADrS_frg[((it + 1, j), 0), 0, 0],\n                        ),\n                        (\n                            tTMEM_LOADrG_frg[((it + 0, j), 0), 0, 0],\n                            tTMEM_LOADrG_frg[((it + 1, j), 0), 0, 0],\n                        ),\n                    )\n\n                s_vec = tTMEM_LOADrS_frg[((None, j), 0), 0, 0].load()\n                tTMEM_STORErS_x4_e_frg[None, j].store(s_vec.to(self.q_dtype))\n\n            # store\n            cute.copy(tiled_tmem_store, tTMEM_STORErS_x4, tTMEM_STOREtO_i)\n            cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def load_q_epi(\n        self,\n        thr_mma: cute.ThrMma,\n        sQ: cute.Tensor,\n        tOut: cute.Tensor,\n        val: cutlass.Float32,  # exp(cumsum_gate) for per-token gating\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Load Q from smem, apply per-token gate.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        sQ_frag = cute.logical_divide(sQ, (((None, 8), None)))\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 64\n        corr_tile_size_f32 = corr_tile_size // 2\n\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_STOREcS_f16 = thr_tmem_store.partition_S(cIn_i)\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n        tTMEM_STORErS_x8 = cute.make_rmem_tensor(tTMEM_STOREcS_f16.shape, self.i_dtype)\n        tTMEM_STORErS_x8_e = cute.make_tensor(\n            cute.recast_ptr(tTMEM_STORErS.iterator, dtype=self.i_dtype),\n            tTMEM_STORErS_x8.layout,\n        )\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size_f32, tTMEM_STOREtO.layout\n            )\n\n            frg_tile = 8\n            tTMEM_STORErS_x8_e_frag = cute.logical_divide(\n                tTMEM_STORErS_x8_e, cute.make_layout(frg_tile)\n            )\n            for col in cutlass.range_constexpr(0, 8):\n                load_row = thread_idx\n                load_col = col\n                curr_val_ssa = sQ_frag[\n                    (load_row, (None, load_col % 2)), 0, (load_col // 2, i), 0\n                ].load()\n                tTMEM_STORErS_x8_e_frag[None, col].store(\n                    (curr_val_ssa * val).to(self.i_dtype)\n                )\n            # store\n            if cutlass.const_expr(mask):\n                if thread_idx >= tail_count:\n                    tTMEM_STORErS_x8_e_frag.fill(self.i_dtype(0))\n            cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n\n        cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def store_k_epi(\n        self,\n        thr_mma: cute.ThrMma,\n        sK: cute.Tensor,\n        tOut: cute.Tensor,\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Load K from smem and store to TMEM.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        sK_frag = cute.logical_divide(sK, (((None, 8), None)))\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 64\n        corr_tile_size_f32 = corr_tile_size // 2\n\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size_f32))\n        )\n\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size_f32)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_STOREcS_f16 = thr_tmem_store.partition_S(cIn_i)\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n        tTMEM_STORErS_x8 = cute.make_rmem_tensor(tTMEM_STOREcS_f16.shape, self.i_dtype)\n        tTMEM_STORErS_x8_e = cute.make_tensor(\n            cute.recast_ptr(tTMEM_STORErS.iterator, dtype=self.i_dtype),\n            tTMEM_STORErS_x8.layout,\n        )\n        frg_tile = 8\n        tTMEM_STORErS_x8_e_frag = cute.logical_divide(\n            tTMEM_STORErS_x8_e, cute.make_layout(frg_tile)\n        )\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size_f32, tTMEM_STOREtO.layout\n            )\n\n            for col in cutlass.range_constexpr(0, 8):\n                load_row = thread_idx\n\n                load_col = col\n                curr_val_ssa = sK_frag[\n                    (load_row, (None, load_col % 2)), 0, (load_col // 2, i), 0\n                ].load()\n                tTMEM_STORErS_x8_e_frag[None, col].store(curr_val_ssa)\n\n            # store\n            if cutlass.const_expr(mask):\n                if thread_idx >= tail_count:\n                    tTMEM_STORErS_x8_e_frag.fill(self.i_dtype(0))\n\n            cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n        cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def reverse_smem_sub(\n        self,\n        reverse_result: cute.Tensor,\n        sIvt: cute.Tensor,\n    ):\n        \"\"\"Compute the inverse of a 32x32 sub-block.\"\"\"\n        lane_id = cute.arch.lane_idx()\n        sub_widx = cute.arch.warp_idx() % 4\n\n        reverse_result.fill(self.acc_dtype(0))\n\n        for row in cutlass.range_constexpr(1, 32, unroll=1):\n            for k in cutlass.range(1, row):\n                row_i_k = sIvt[(k, row), sub_widx]\n                reverse_result[row] -= reverse_result[k] * row_i_k\n            row_i_lane = self.acc_dtype(0)\n            if lane_id < row:\n                row_i_lane = sIvt[(lane_id, row), sub_widx]\n            reverse_result[row] -= row_i_lane\n        reverse_result[lane_id] = self.acc_dtype(1)\n\n    @cute.jit\n    def store_ivt_smem_l0_ss_a(\n        self,\n        reverse_result: cute.Tensor,\n        sReg: cute.Tensor,\n        sInvertSubSSL0A: cute.Tensor,\n    ):\n        \"\"\"Store 32x32 sub-inverse results to smem.\"\"\"\n\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n\n        sub_widx = widx % 4\n\n        # store sub result to shared memory\n        # (((4,128),8))\n        for row_bid in cutlass.range_constexpr(4):\n            for col_bid in cutlass.range_constexpr(8):\n                row_d = (lane_id // 4 + col_bid) % 8\n                row = row_bid * 8 + row_d\n                col_id = lane_id // 4\n                col_sub_id = lane_id % 4\n                sReg[(col_sub_id, sub_widx * 32 + row), col_id] = reverse_result[row]\n\n        cutlass.cute.arch.sync_warp()\n\n        if sub_widx == 1 or sub_widx == 3:\n            sub_id_row = sub_widx // 2\n            sInvertSubSSL0A_frag = cute.logical_divide(\n                sInvertSubSSL0A, ((None, 4), None)\n            )\n            for col in cutlass.range_constexpr(8):\n                sInvertSubSSL0A_frag[\n                    (sub_id_row * 32 + lane_id, (None, col % 2)), 0, col // 2, 0\n                ].store(sReg[(None, tidx % 128), col].load())\n\n    @cute.jit\n    def store_ivt_smem_l0_ss_b(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        sInvertSubSSL0B: cute.Tensor,\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        # bidx, bidy, _ = cute.arch.block_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        sub_widx = widx % 4\n\n        # load Tmem\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 32  # must <= 32\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        # Load In\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        sub_tile_size = 8\n        tmem_frag = cute.logical_divide(tTMEM_LOADrS, ((sub_tile_size, None), None))\n        sInvertSubSSL0B_frag = cute.logical_divide(\n            sInvertSubSSL0B, ((sub_tile_size, None), None)\n        )\n\n        # tile 0\n        tile_frags = corr_tile_size // sub_tile_size\n        for i in cutlass.range_constexpr(32 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n            if sub_widx == 1:\n                idx = (i * corr_tile_size) // sub_tile_size\n                for j in cutlass.range_constexpr(tile_frags):\n                    col_true = (idx + j) % 8\n                    # todo: remove smem bank conflict\n                    sInvertSubSSL0B_frag[\n                        ((None, (col_true, 0)), lane_id % 8), 0, lane_id // 8, 0\n                    ].store(tmem_frag[((None, j), 0), 0, 0].load())\n\n        # tile 2\n        for i in cutlass.range_constexpr(32 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + 64 + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n            if sub_widx == 3:\n                idx = (i * corr_tile_size) // sub_tile_size\n                for j in cutlass.range_constexpr(tile_frags):\n                    col_true = (idx + j) % 8\n                    # todo: remove smem bank conflict\n                    sInvertSubSSL0B_frag[\n                        ((None, (col_true, 1)), lane_id % 8), 0, lane_id // 8, 0\n                    ].store(tmem_frag[((None, j), 0), 0, 0].load())\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_ivt_smem_l1_ss_b(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        sInvertSubSSL1B: cute.Tensor,\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        # bidx, bidy, _ = cute.arch.block_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        sub_widx = widx % 4\n\n        # load Tmem\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 8\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        # Load In\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_LOADrS = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        # tile 0\n        tTMEM_LOADtO_i = cute.make_tensor(tTMEM_LOADtO.iterator, tTMEM_LOADtO.layout)\n\n        cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n        cute.arch.fence_view_async_tmem_load()\n        sub_tile_size = 8\n        tmem_frag = cute.logical_divide(tTMEM_LOADrS, ((sub_tile_size, None), None))\n        sInvertSubSSL1B_frag = cute.logical_divide(\n            sInvertSubSSL1B, ((sub_tile_size, None), None)\n        )\n        tile_frags = corr_tile_size // sub_tile_size\n        if sub_widx == 2 or sub_widx == 3:\n            sub_id_row = sub_widx - 2\n            for col in cutlass.range_constexpr(tile_frags):\n                col_true = (lane_id + col) % (tile_frags)\n                sInvertSubSSL1B_frag[\n                    ((None, (col_true, 0)), lane_id % 8),\n                    0,\n                    lane_id // 8 + sub_id_row * 4,\n                    0,\n                ].store(tmem_frag[((None, col_true), 0), 0, 0].load())\n\n        # tile 0\n        for i in cutlass.range_constexpr(32 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n            if sub_widx == 2 or sub_widx == 3:\n                sub_id_row = sub_widx - 2\n                idx = (i * corr_tile_size) // sub_tile_size\n                for j in cutlass.range_constexpr(tile_frags):\n                    col_true = (idx + j) % 8\n                    # todo: remove smem bank conflict\n                    sInvertSubSSL1B_frag[\n                        ((None, (col_true, 0)), lane_id % 8),\n                        0,\n                        lane_id // 8 + sub_id_row * 4,\n                        0,\n                    ].store(tmem_frag[((None, j), 0), 0, 0].load())\n        # tile 1\n        for i in cutlass.range_constexpr(32 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + 32 + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n            if sub_widx == 2 or sub_widx == 3:\n                sub_id_row = sub_widx - 2\n                idx = (i * corr_tile_size) // sub_tile_size\n                for j in cutlass.range_constexpr(tile_frags):\n                    col_true = (idx + j) % 8\n                    # todo: remove smem bank conflict\n                    sInvertSubSSL1B_frag[\n                        ((None, (col_true, 1)), lane_id % 8),\n                        0,\n                        lane_id // 8 + sub_id_row * 4,\n                        0,\n                    ].store(tmem_frag[((None, j), 0), 0, 0].load())\n\n    @cute.jit\n    def store_ivt_p1(\n        self,\n        sReg: cute.Tensor,\n        sInvertSubTSL0B: cute.Tensor,\n    ):\n        \"\"\"Store sub-inverse register results p1 to smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n\n        sub_widx = widx % 4\n\n        sInvertSubTSL0B_frag = cute.logical_divide(sInvertSubTSL0B, ((4, None), None))\n        if sub_widx == 0 or sub_widx == 2:\n            sub_id_row = sub_widx // 2\n            for col in cutlass.range_constexpr(8):\n                col_true = (lane_id + col) % 8\n                sInvertSubTSL0B_frag[\n                    ((None, (col_true, sub_id_row)), lane_id % 8), 0, lane_id // 8, 0\n                ].store(sReg[(None, tidx % 128), col_true].load())\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_ivt_p2(\n        self,\n        sReg: cute.Tensor,\n        sInvertSubSSL1A: cute.Tensor,\n    ):\n        \"\"\"Store sub-inverse register results p2 to smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n\n        sub_widx = widx % 4\n        sInvertSubSSL1A_frag = cute.logical_divide(sInvertSubSSL1A, ((None, 4), None))\n        zeros = cute.zeros_like(cute.make_layout((4, 1)), self.acc_dtype)\n        if sub_widx == 2 or sub_widx == 3:\n            sub_id_row = sub_widx - 2\n            for col in cutlass.range_constexpr(8):\n                sInvertSubSSL1A_frag[\n                    (sub_id_row * 32 + lane_id, (None, col % 2)),\n                    0,\n                    (col // 2, sub_id_row),\n                    0,\n                ].store(sReg[(None, tidx % 128), col].load())\n\n        if sub_widx == 0 or sub_widx == 1:\n            for col in cutlass.range_constexpr(4):\n                col_true = col + sub_widx * 4\n                sInvertSubSSL1A_frag[\n                    (lane_id, (None, col_true % 2)), 0, (col_true // 2, 1), 0\n                ].store(zeros)\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_ivt_p3(\n        self,\n        sReg: cute.Tensor,\n        sInvertSubTSL1B: cute.Tensor,\n    ):\n        \"\"\"Store sub-inverse register results p3 to smem .\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n\n        sub_widx = widx % 4\n        sInvertSubTSL1B_frag = cute.logical_divide(sInvertSubTSL1B, ((4, None), None))\n        if sub_widx == 0 or sub_widx == 1:\n            sub_id_row = sub_widx\n            for col in cutlass.range_constexpr(8):\n                col_true = (lane_id + col) % 8\n                sInvertSubTSL1B_frag[\n                    ((None, (col_true, sub_id_row)), lane_id % 8),\n                    0,\n                    lane_id // 8 + 4 * sub_id_row,\n                    0,\n                ].store(sReg[(None, tidx % 128), col_true].load())\n        zeros = cute.zeros_like(cute.make_layout((4, 1)), self.acc_dtype)\n\n        if sub_widx == 2 or sub_widx == 3:\n            sub_id_row = sub_widx - 2\n            for col in cutlass.range_constexpr(4):\n                col_true = (lane_id + col + sub_id_row * 4) % 8\n                sInvertSubTSL1B_frag[\n                    ((None, (col_true, 1)), lane_id % 8), 0, lane_id // 8 + 0, 0\n                ].store(zeros)\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def load_store_tmem_tune(\n        self,\n        thr_mma: cute.ThrMma,\n        tIn: cute.Tensor,\n        tOut: cute.Tensor,  # unused utility for TMEM round-trip debugging\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 16\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMrO = cute.make_rmem_tensor(\n            (tTMEM_LOADcO.shape, 128 // corr_tile_size), self.acc_dtype\n        )\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMrO_i_ = tTMrO[None, i]\n            tTMrO_i_layout = cute.composition(\n                tTMrO_i_.layout, cute.make_layout(tTMrO.shape[0])\n            )\n            tTMrO_i = cute.make_tensor(tTMrO_i_.iterator, tTMrO_i_layout)\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout\n            )\n\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMrO_i)\n\n            for j in cutlass.range_constexpr(0, cute.size(tTMrO_i), 2):\n                tTMrO_i[j], tTMrO_i[j + 1] = cute.arch.mul_packed_f32x2(\n                    (tTMrO_i[j], tTMrO_i[j + 1]),\n                    (cutlass.Float32(1), cutlass.Float32(1)),\n                )\n\n            # store\n            cute.copy(tiled_tmem_store, tTMrO_i, tTMEM_STOREtO_i)\n\n    @cute.jit\n    def read_tmem_128(\n        self,\n        tIn: cute.Tensor,\n    ):\n        \"\"\"Read a 128-element vector from TMEM into registers.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tIn_layout = cute.composition(tIn.layout, cute.make_layout((tIn.shape)))\n        tIn = cute.make_tensor(tIn.iterator, tIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)),\n            self.acc_dtype,\n        )\n\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tIn)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tIn)\n        tTR_cO = thr_copy_t2r.partition_D(tIn)\n\n        tTR_rO = cute.make_rmem_tensor(tTR_cO.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n        tTR_rO = cute.group_modes(tTR_rO, 1, cute.rank(tTR_rO))\n        cute.copy(tiled_copy_t2r, tTR_tO, tTR_rO)\n        cute.arch.fence_view_async_tmem_load()\n\n        return tTR_rO\n\n    @cute.jit\n    def load_v(\n        self,\n        tIn: cute.Tensor,\n        sNewV: cute.Tensor,\n    ):\n        \"\"\"Load V_new from TMEM, convert to f16, store to smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tIn_layout = cute.composition(tIn.layout, cute.make_layout((tIn.shape)))\n        tIn = cute.make_tensor(tIn.iterator, tIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(32)),\n            self.acc_dtype,\n        )\n\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tIn)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n\n        tTR_tO = thr_copy_t2r.partition_S(tIn)\n        tTR_cO = thr_copy_t2r.partition_D(tIn)\n\n        tTR_rO = cute.make_rmem_tensor(tTR_cO.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n        tTR_rO = cute.group_modes(tTR_rO, 1, cute.rank(tTR_rO))\n        cute.copy(tiled_copy_t2r, tTR_tO, tTR_rO)\n        cute.arch.fence_view_async_tmem_load()\n\n        tTR_rO_e = cute.make_rmem_tensor(tTR_cO.shape, self.i_dtype)\n        frg_cnt = 16\n        frg_tile = cute.size(tTR_rO) // frg_cnt\n        tTR_rO_frg = cute.logical_divide(tTR_rO, cute.make_layout(frg_tile))\n        tTR_rO_e_frg = cute.logical_divide(tTR_rO_e, cute.make_layout(frg_tile))\n        for j in cutlass.range_constexpr(frg_cnt):\n            r_vec = tTR_rO_frg[None, j].load()\n            tTR_rO_e_frg[None, j].store(r_vec.to(self.i_dtype))\n\n        sNewV_frg = cute.logical_divide(sNewV, cute.make_layout(frg_tile))\n        for it in cutlass.range_constexpr(0, 16):\n            sNewV_frg[None, (it, thread_idx)].store(tTR_rO_e_frg[None, it].load())\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def load_ivt_result(\n        self,\n        tIn: cute.Tensor,\n        sD: cute.Tensor,\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        lane_id = tidx % 32\n        warp_id = cute.arch.warp_idx() % 4\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tIn_layout = cute.composition(tIn.layout, cute.make_layout((tIn.shape)))\n        tIn = cute.make_tensor(tIn.iterator, tIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld16x256bOp(tcgen05.copy.Repetition(4)),\n            self.acc_dtype,\n        )\n\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tIn)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tIn)\n        tTR_cO = thr_copy_t2r.partition_D(tIn)\n\n        tTR_rO = cute.make_rmem_tensor(tTR_cO.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n        tTR_rO = cute.group_modes(tTR_rO, 1, cute.rank(tTR_rO))\n        cute.copy(tiled_copy_t2r, tTR_tO, tTR_rO)\n        cute.arch.fence_view_async_tmem_load()\n\n        tTR_rO_e = cute.make_rmem_tensor(tTR_cO.shape, self.q_dtype)\n\n        frg_cnt = 2\n        frg_tile = cute.size(tTR_rO) // frg_cnt\n        tTR_rO_frg = cute.logical_divide(tTR_rO, cute.make_layout(frg_tile))\n        tTR_rO_e_frg = cute.logical_divide(tTR_rO_e, cute.make_layout(frg_tile))\n        for j in cutlass.range_constexpr(frg_cnt):\n            r_vec = -tTR_rO_frg[None, j].load()\n            tTR_rO_e_frg[None, j].store(r_vec.to(self.q_dtype))\n\n        tTR_rO_e_f32 = cute.recast_tensor(src=tTR_rO_e, dtype=cutlass.Float32)\n\n        for it in cutlass.range_constexpr(0, 8):\n            sD[\n                ((64 + warp_id * 16 + (lane_id // 4) + 0), (lane_id % 4, it % 2)),\n                it // 2,\n            ] = tTR_rO_e_f32[it * 2]\n            sD[\n                ((64 + warp_id * 16 + (lane_id // 4) + 8), (lane_id % 4, it % 2)),\n                it // 2,\n            ] = tTR_rO_e_f32[it * 2 + 1]\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def apply_gamma_beta(\n        self,\n        thr_mma: cute.ThrMma,\n        sIvt: cute.Tensor,\n        tIn: cute.Tensor,\n        beta_val: cutlass.Float32,\n        tGamma: cute.Tensor,\n    ):\n        \"\"\"Apply gamma*beta to KK^T in TMEM.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        lane_id = tidx % 32\n        warp_id = cute.arch.warp_idx() % 4\n        sub_widx = warp_id % 4\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 32  # only 8  or 32\n        tIn_i_layout = cute.composition(\n            tIn.layout, cute.make_layout((128, corr_tile_size))\n        )\n        cIn_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tIn_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n\n        tOut_i = cute.make_tensor(tIn.iterator, tIn_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cIn_i_layout)\n\n        tGamma_i = cute.make_tensor(tGamma.iterator, tIn_i_layout)\n        cIn_i = cute.make_tensor(cIn.iterator, cIn_i_layout)\n\n        tmem_load_atom = cute.make_copy_atom(\n            tcgen05.copy.Ld32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n\n        # Load In\n        tiled_tmem_load = tcgen05.make_tmem_copy(tmem_load_atom, tIn_i)\n        thr_tmem_load = tiled_tmem_load.get_slice(thread_idx)\n\n        # Load Gamma\n        tiled_tmem_load_gamma = tcgen05.make_tmem_copy(tmem_load_atom, tGamma_i)\n        thr_tmem_load_gamma = tiled_tmem_load_gamma.get_slice(thread_idx)\n\n        tTMEM_LOADtO = thr_tmem_load.partition_S(tIn_i)\n        tTMEM_LOADcO = thr_tmem_load.partition_D(cIn_i)\n\n        tTMEM_LOADtG = thr_tmem_load_gamma.partition_S(tGamma_i)\n        tTMEM_LOADrG = cute.make_rmem_tensor(tTMEM_LOADcO.shape, self.acc_dtype)\n\n        tTMEM_LOADrS = cute.make_tensor(\n            cute.recast_ptr(tTMEM_STORErS.iterator, dtype=self.acc_dtype),\n            tTMEM_LOADrG.layout,\n        )\n\n        frg_tile = 4\n\n        # Store to smem\n        # ((32, 32), 4)\n        lower_D_frag = cute.logical_divide(tTMEM_STORErS, ((4, None), None))\n        sIvt_frag = cute.logical_divide(sIvt, ((4, None), None))\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_LOADtO_i = cute.make_tensor(\n                tTMEM_LOADtO.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n            tTMEM_LOADtG_i = cute.make_tensor(\n                tTMEM_LOADtG.iterator + i * corr_tile_size, tTMEM_LOADtO.layout\n            )\n\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout\n            )\n\n            cute.copy(tiled_tmem_load_gamma, tTMEM_LOADtG_i, tTMEM_LOADrG)\n            each_iter = corr_tile_size // frg_tile\n            tTMEM_LOADrG_frg = cute.logical_divide(\n                tTMEM_LOADrG, ((frg_tile, None), None)\n            )\n            for j in cutlass.range_constexpr(each_iter):\n                for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                    (\n                        tTMEM_LOADrG_frg[((inner_idx + 0, j), i), 0, 0],\n                        tTMEM_LOADrG_frg[((inner_idx + 1, j), i), 0, 0],\n                    ) = cute.arch.mul_packed_f32x2(\n                        (\n                            tTMEM_LOADrG_frg[((inner_idx + 0, j), i), 0, 0],\n                            tTMEM_LOADrG_frg[((inner_idx + 1, j), i), 0, 0],\n                        ),\n                        (\n                            beta_val,\n                            beta_val,\n                        ),\n                    )\n            cute.copy(tiled_tmem_load, tTMEM_LOADtO_i, tTMEM_LOADrS)\n            cute.arch.fence_view_async_tmem_load()\n\n            tTMEM_LOADrS_frg = cute.logical_divide(\n                tTMEM_LOADrS, ((frg_tile, None), None)\n            )\n\n            if (i * corr_tile_size) < ((sub_widx + 1) * 32):\n                for j in cutlass.range_constexpr(each_iter):\n                    for inner_idx in cutlass.range_constexpr(0, frg_tile, 2):\n                        (\n                            tTMEM_LOADrS_frg[((inner_idx + 0, j), i), 0, 0],\n                            tTMEM_LOADrS_frg[((inner_idx + 1, j), i), 0, 0],\n                        ) = cute.arch.mul_packed_f32x2(\n                            (\n                                tTMEM_LOADrS_frg[((inner_idx + 0, j), i), 0, 0],\n                                tTMEM_LOADrS_frg[((inner_idx + 1, j), i), 0, 0],\n                            ),\n                            (\n                                tTMEM_LOADrG_frg[((inner_idx + 0, j), i), 0, 0],\n                                tTMEM_LOADrG_frg[((inner_idx + 1, j), i), 0, 0],\n                            ),\n                        )\n            cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n\n            tile_frags = corr_tile_size // 4\n            if (i * corr_tile_size) >= sub_widx * 32 and (i * corr_tile_size) < (\n                sub_widx + 1\n            ) * 32:\n                idx = (i * corr_tile_size - sub_widx * 32) // 4\n                for j in cutlass.range_constexpr(tile_frags):\n                    true_col = j + idx\n                    sIvt_frag[((None, true_col), lane_id), sub_widx].store(\n                        lower_D_frag[((None, j), 0), 0, 0].load()\n                    )\n\n    @cute.jit\n    def compute_gamma_tmem(\n        self,\n        val: cutlass.Float32,\n        sGateCumsum: cute.Tensor,\n        thr_mma: cute.ThrMma,\n        tOut: cute.Tensor,\n        bar_id: Int32,\n        mask: cutlass.Constexpr[cutlass.Boolean] = False,\n        tail_count: Int32 = 128,\n    ):\n        \"\"\"Build the 128x128 causal gamma matrix in TMEM: gamma[i,j] = exp(cumsum[i] - cumsum[j]) for j <= i.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        thread_idx = tidx % 128\n\n        cute.arch.barrier(\n            barrier_id=bar_id,\n            number_of_threads=len(self.cudacore_warp_ids) * 32,\n        )\n\n        cIn = cute.make_identity_tensor((128, 128))\n        tOcO = thr_mma.partition_C(cIn)\n\n        corr_tile_size = 128\n\n        cOut_i_layout = cute.composition(\n            tOcO.layout, cute.make_layout((128, corr_tile_size))\n        )\n        tOut_i_layout = cute.composition(\n            tOut.layout, cute.make_layout((128, corr_tile_size))\n        )\n\n        tOut_i = cute.make_tensor(tOut.iterator, tOut_i_layout)\n        cOut_i = cute.make_tensor(tOcO.iterator, cOut_i_layout)\n\n        tmem_store_atom = cute.make_copy_atom(\n            tcgen05.copy.St32x32bOp(tcgen05.copy.Repetition(corr_tile_size)),\n            self.acc_dtype,\n        )\n\n        tiled_tmem_store = tcgen05.make_tmem_copy(tmem_store_atom, tOut_i)\n        thr_tmem_store = tiled_tmem_store.get_slice(thread_idx)\n\n        tTMEM_STOREcS = thr_tmem_store.partition_S(cOut_i)\n        tTMEM_STOREtO = thr_tmem_store.partition_D(tOut_i)\n\n        tTMEM_STORErS = cute.make_rmem_tensor(tTMEM_STOREcS.shape, self.acc_dtype)\n\n        frg_tile = 32\n        sGateCumsum_tile = cute.flat_divide(\n            sGateCumsum, cute.make_layout(corr_tile_size)\n        )\n        sGateCumsum_frag = cute.logical_divide(sGateCumsum_tile, (frg_tile, None))\n\n        zeros = cute.zeros_like(cute.make_layout((frg_tile, 1)), self.acc_dtype)\n\n        for i in cutlass.range_constexpr(128 // corr_tile_size):\n            tTMEM_STOREtO_i = cute.make_tensor(\n                tTMEM_STOREtO.iterator + i * corr_tile_size, tTMEM_STOREtO.layout\n            )\n\n            tTMEM_STORErS_frag = cute.logical_divide(\n                tTMEM_STORErS, cute.make_layout(frg_tile)\n            )\n            for it in cutlass.range_constexpr(corr_tile_size // frg_tile):\n                tile_offset = i * corr_tile_size + it * frg_tile\n\n                if (\n                    (\n                        tile_offset <= thread_idx\n                        and tile_offset < tail_count\n                        and thread_idx < tail_count\n                    )\n                    if cutlass.const_expr(mask)\n                    else (tile_offset <= thread_idx)\n                ):\n                    curr_val_frag_ssa = sGateCumsum_frag[(None, it), i].load()\n\n                    new_val_frag = cute.math.exp(val - curr_val_frag_ssa, fastmath=True)\n\n                    for inner_idx in cutlass.range_constexpr(0, frg_tile):\n                        offset = tile_offset + inner_idx\n                        curr_val = new_val_frag[inner_idx]\n\n                        if offset <= thread_idx:\n                            tTMEM_STORErS_frag[inner_idx, it] = curr_val\n                        else:\n                            tTMEM_STORErS_frag[inner_idx, it] = cutlass.Float32(0)\n                else:\n                    tTMEM_STORErS_frag[None, it].store(zeros)\n\n            # store\n            cute.copy(tiled_tmem_store, tTMEM_STORErS, tTMEM_STOREtO_i)\n        cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def chunk_local_cumsum(\n        self,\n        sGate: cute.Tensor,\n        sGateCumsum: cute.Tensor,\n        bar_id: Int32,\n    ) -> cutlass.Float32:\n        \"\"\"Compute inclusive prefix sum of gate values within a 128-token chunk.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        lane_id = tidx % 32\n        warp_id = cute.arch.warp_idx() % 4\n        tidx_in_group = tidx % 128\n\n        val = sGate[tidx_in_group]\n        stride = 1\n        clamp_value = 0\n        while stride < 32:\n            shfl_value = cute.arch.shuffle_sync_op(\n                value=val,\n                offset=stride,\n                mask_and_clamp=clamp_value,\n                kind=nvvm.ShflKind.up,\n            )\n            if lane_id >= stride:\n                val += shfl_value\n\n            stride = stride << 1\n        if lane_id == 31:\n            sGateCumsum[warp_id] = val\n\n        cute.arch.barrier(\n            barrier_id=bar_id,\n            number_of_threads=len(self.cudacore_warp_ids) * 32,\n        )\n\n        if warp_id == 1:\n            pre_warp_val = sGateCumsum[0]\n            val = val + pre_warp_val\n        if warp_id == 2:\n            sGateCumsum_f2 = cute.flat_divide(sGateCumsum, (2, 1))\n            warp_sum = sGateCumsum_f2[None, 0, 0, 0]\n            pre_warp_val = warp_sum[0] + warp_sum[1]\n            val = val + pre_warp_val\n        if warp_id == 3:\n            sGateCumsum_f4 = cute.flat_divide(sGateCumsum, (4, 1))\n            warp_sum = sGateCumsum_f4[None, 0, 0, 0]\n            pre_warp_val = warp_sum[0] + warp_sum[1] + warp_sum[2]\n            val = val + pre_warp_val\n\n        cute.arch.barrier(\n            barrier_id=bar_id,\n            number_of_threads=len(self.cudacore_warp_ids) * 32,\n        )\n\n        sGateCumsum[tidx_in_group] = val\n\n        return val\n\n    @cute.jit\n    def save_tmem(\n        self,\n        tSIn: cute.Tensor,\n        sD: cute.Tensor,\n    ) -> cute.Tensor:\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        sub_widx = widx % 4\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tSIn_layout = cute.composition(tSIn.layout, cute.make_layout((tSIn.shape)))\n        tSIn0 = cute.make_tensor(tSIn.iterator, tSIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld16x256bOp(tcgen05.copy.Repetition(4)),\n            self.acc_dtype,\n        )\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tSIn0)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tSIn0)\n        tTR_cO = thr_copy_t2r.partition_D(tSIn0)\n        tTR_cO_one_iter = tTR_cO[None, 0, 0, 0]\n        tTR_rO = cute.make_rmem_tensor(tTR_cO_one_iter.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n\n        tTR_rO_e = cute.make_rmem_tensor(tTR_rO.shape, self.q_dtype)\n        frg_cnt = 2\n        frg_tile = cute.size(tTR_rO) // frg_cnt\n        tTR_rO_frg = cute.logical_divide(tTR_rO, cute.make_layout(frg_tile))\n        tTR_rO_e_frg = cute.logical_divide(tTR_rO_e, cute.make_layout(frg_tile))\n        tTR_rO_e_f32 = cute.recast_tensor(src=tTR_rO_e, dtype=cutlass.Float32)\n        for subtile_idx in cutlass.range_constexpr(2):\n            tTR_tO_mn = tTR_tO[(None, subtile_idx)]\n            cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)\n            cute.arch.fence_view_async_tmem_load()\n\n            if (sub_widx == 0 or sub_widx == 1) and subtile_idx == 0:\n                for j in cutlass.range_constexpr(frg_cnt):\n                    r_vec = -tTR_rO_frg[None, j].load()\n                    tTR_rO_e_frg[None, j].store(r_vec.to(self.q_dtype))\n\n                for it in cutlass.range_constexpr(0, 4):\n                    sD[\n                        (\n                            (\n                                32\n                                + (sub_widx // 2) * 64\n                                + (sub_widx % 2) * 16\n                                + (lane_id // 4)\n                                + 0\n                            ),\n                            (lane_id % 4, it % 2),\n                        ),\n                        it // 2 + (sub_widx // 2) * 4,\n                    ] = tTR_rO_e_f32[it * 2]\n                    sD[\n                        (\n                            (\n                                32\n                                + (sub_widx // 2) * 64\n                                + (sub_widx % 2) * 16\n                                + (lane_id // 4)\n                                + 8\n                            ),\n                            (lane_id % 4, it % 2),\n                        ),\n                        it // 2 + (sub_widx // 2) * 4,\n                    ] = tTR_rO_e_f32[it * 2 + 1]\n\n            if (sub_widx == 2 or sub_widx == 3) and subtile_idx == 1:\n                for j in cutlass.range_constexpr(frg_cnt):\n                    r_vec = -tTR_rO_frg[None, j].load()\n                    tTR_rO_e_frg[None, j].store(r_vec.to(self.q_dtype))\n\n                for it in cutlass.range_constexpr(0, 4):\n                    sD[\n                        (\n                            (\n                                32\n                                + (sub_widx // 2) * 64\n                                + (sub_widx % 2) * 16\n                                + (lane_id // 4)\n                                + 0\n                            ),\n                            (lane_id % 4, it % 2),\n                        ),\n                        it // 2 + (sub_widx // 2) * 4,\n                    ] = tTR_rO_e_f32[it * 2]\n                    sD[\n                        (\n                            (\n                                32\n                                + (sub_widx // 2) * 64\n                                + (sub_widx % 2) * 16\n                                + (lane_id // 4)\n                                + 8\n                            ),\n                            (lane_id % 4, it % 2),\n                        ),\n                        it // 2 + (sub_widx // 2) * 4,\n                    ] = tTR_rO_e_f32[it * 2 + 1]\n\n    @cute.jit\n    def load_ivt_ts_l0(\n        self,\n        tSIn: cute.Tensor,\n        sInvertSubSSL1A: cute.Tensor,\n        sInvertSubTSL1B: cute.Tensor,\n    ) -> cute.Tensor:\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        sub_widx = widx % 4\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tSIn_layout = cute.composition(tSIn.layout, cute.make_layout((tSIn.shape)))\n        tSIn0 = cute.make_tensor(tSIn.iterator, tSIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld16x128bOp(tcgen05.copy.Repetition(8)),  # todo\n            self.acc_dtype,\n        )\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tSIn0)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tSIn0)\n        tTR_cO = thr_copy_t2r.partition_D(tSIn0)\n        tTR_cO_one_iter = tTR_cO[None, 0, 0, 0]\n        tTR_rO = cute.make_rmem_tensor(tTR_cO_one_iter.shape, self.acc_dtype)\n\n        tTR_rO_s = cute.make_tensor(\n            cute.recast_ptr(tTR_rO.iterator, dtype=self.acc_dtype),\n            cute.shape(tTR_cO_one_iter)[0],\n        )\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n\n        for subtile_idx in cutlass.range_constexpr(2):\n            tTR_tO_mn = tTR_tO[(None, subtile_idx)]\n            cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)\n            cute.arch.fence_view_async_tmem_load()\n\n            if (sub_widx == 0 or sub_widx == 1) and subtile_idx == 0:\n                sInvertSubTSL1B_frag = cute.logical_divide(\n                    sInvertSubTSL1B, ((4, None), None)\n                )\n                sub_id_row = sub_widx\n                for col in cutlass.range_constexpr(0, 8):\n                    col_true = (lane_id // 4 + col) % 8\n                    sInvertSubTSL1B_frag[\n                        ((lane_id % 4, (col_true, 0)), lane_id // 4),\n                        0,\n                        4 + sub_id_row * 2 + 0,\n                        0,\n                    ] = -tTR_rO_s[(0, col_true), 0]\n                    sInvertSubTSL1B_frag[\n                        ((lane_id % 4, (col_true, 0)), lane_id // 4),\n                        0,\n                        4 + sub_id_row * 2 + 1,\n                        0,\n                    ] = -tTR_rO_s[(1, col_true), 0]\n            if (sub_widx == 2 or sub_widx == 3) and subtile_idx == 1:\n                tTR_rO_s_frag_f1 = cute.logical_divide(\n                    cute.flatten(tTR_rO_s[None, 0]), (1, None)\n                )\n                sInvertSubSSL1A_frag_f1 = cute.logical_divide(\n                    sInvertSubSSL1A, ((None, 1), None)\n                )\n                sub_id_row = sub_widx - 2\n                for it in cutlass.range_constexpr(0, 8):\n                    col_offset = it % 2 * 4\n                    sInvertSubSSL1A_frag_f1[\n                        (\n                            32 + sub_id_row * 16 + 0 + lane_id // 4,\n                            (None, col_offset + lane_id % 4),\n                        ),\n                        0,\n                        (it // 2, 0),\n                        0,\n                    ].store(-tTR_rO_s_frag_f1[(None, 0), it].load())\n                    sInvertSubSSL1A_frag_f1[\n                        (\n                            32 + sub_id_row * 16 + 8 + lane_id // 4,\n                            (None, col_offset + lane_id % 4),\n                        ),\n                        0,\n                        (it // 2, 0),\n                        0,\n                    ].store(-tTR_rO_s_frag_f1[(None, 1), it].load())\n\n        cute.arch.fence_proxy(\n            cute.arch.ProxyKind.async_shared,\n            space=cute.arch.SharedSpace.shared_cta,\n        )\n\n    @cute.jit\n    def store_ivt_c(\n        self,\n        sD: cute.Tensor,\n    ):\n        \"\"\"Zero out off-diagonal blocks in the assembled inverse matrix (block identity structure).\"\"\"\n        widx = cute.arch.warp_idx()\n        lane_id = cute.arch.lane_idx()\n        sub_widx = widx % 4\n\n        zeros = cute.zeros_like(cute.make_layout((4, 1)), self.acc_dtype)\n        for it in cutlass.range_constexpr(0, 4):\n            row = sub_widx // 2 * 32 + lane_id\n            col_block_inner = it % 2\n            col_block = 4 + (sub_widx % 2) * 2 + it // 2\n            sD[(row, (None, col_block_inner)), col_block].store(zeros[None, 0])\n        for it in cutlass.range_constexpr(0, 2):\n            row = sub_widx // 2 * 64 + lane_id\n            col_block_inner = sub_widx % 2\n            col_block = (sub_widx // 2) * 4 + 2 + it\n            sD[(row, (None, col_block_inner)), col_block].store(zeros[None, 0])\n\n    @cute.jit\n    def load_ivt_ss_l0(\n        self,\n        tSIn: cute.Tensor,\n        tSOut: cute.Tensor,\n    ):\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        sub_widx = widx % 4\n\n        thread_idx = tidx % (self.threads_per_warp * (len(self.cudacore_warp_ids)))\n\n        tSIn_layout = cute.composition(tSIn.layout, cute.make_layout((tSIn.shape)))\n        tSIn0 = cute.make_tensor(tSIn.iterator, tSIn_layout)\n\n        # Load from tmem\n        copy_atom_t2r = cute.make_copy_atom(\n            tcgen05.copy.Ld16x256bOp(tcgen05.copy.Repetition(4)),  # 4*8 = 32\n            self.acc_dtype,\n        )\n\n        tiled_copy_t2r = tcgen05.make_tmem_copy(copy_atom_t2r, tSIn0)\n        thr_copy_t2r = tiled_copy_t2r.get_slice(thread_idx)\n        tTR_tO = thr_copy_t2r.partition_S(tSIn0)\n        tTR_cO = thr_copy_t2r.partition_D(tSIn0)\n        tTR_cO_one_iter = tTR_cO[(None), 0, 0, 0]\n        tTR_rO = cute.make_rmem_tensor(tTR_cO_one_iter.shape, self.acc_dtype)\n\n        tTR_tO = cute.group_modes(tTR_tO, 1, cute.rank(tTR_tO))\n\n        tSOut_layout = cute.make_layout(\n            (((16, 4), 32), 1, 1), stride=(((65536, 2097152), 1), 0, 0)\n        )\n        tSOut0 = cute.make_tensor(tSOut.iterator, tSOut_layout)\n        copy_atom_r2t = cute.make_copy_atom(\n            tcgen05.copy.St16x256bOp(tcgen05.copy.Repetition(4)),\n            self.acc_dtype,\n        )\n        tiled_copy_r2t = tcgen05.make_tmem_copy(copy_atom_r2t, tSOut0)\n        thr_copy_r2t = tiled_copy_r2t.get_slice(thread_idx)\n        tRT_cO = thr_copy_r2t.partition_S(tSOut0)\n        tRT_tO = thr_copy_r2t.partition_D(tSOut0)\n        tRT_cO_one_iter = tRT_cO[(None), None, 0, 0]  #\n        tRT_rO = cute.make_rmem_tensor(tRT_cO_one_iter.shape, self.acc_dtype)\n\n        for subtile_idx in cutlass.range_constexpr(2):\n            tTR_tO_mn = tTR_tO[(None, subtile_idx)]\n            cute.copy(tiled_copy_t2r, tTR_tO_mn, tTR_rO)\n            cute.arch.fence_view_async_tmem_load()\n\n            if (sub_widx == 0 or sub_widx == 1) and subtile_idx == 0:\n                for eid in cutlass.range_constexpr(16):\n                    tRT_rO[eid] = tTR_rO[eid]\n\n            if (sub_widx == 2 or sub_widx == 3) and subtile_idx == 1:\n                for eid in cutlass.range_constexpr(16):\n                    tRT_rO[eid] = tTR_rO[eid]\n\n        tRT_tO = cute.group_modes(tRT_tO, 2, cute.rank(tRT_tO))\n        for subtile_idx in cutlass.range_constexpr(0, 1):\n            tRT_tO_mn = tRT_tO[(None, None, subtile_idx)]\n            cute.copy(tiled_copy_r2t, tRT_rO, tRT_tO_mn)\n\n        cute.arch.fence_view_async_tmem_store()\n\n    @cute.jit\n    def store_ivt_ad(\n        self,\n        sReg: cute.Tensor,\n        sD: cute.Tensor,\n    ):\n        \"\"\"Store diagonal block inverse (A/D blocks) from registers to smem.\"\"\"\n        tidx, _, _ = cute.arch.thread_idx()\n        widx = cute.arch.warp_idx()\n        sub_widx = widx % 4\n\n        reg_layout = cute.make_layout((4, 2))\n        result_e = cute.make_rmem_tensor(reg_layout.shape, self.acc_dtype)\n        for it in cutlass.range_constexpr(0, 4):\n            result_e[None, 0].store(sReg[(None, tidx % 128), it * 2 + 0].load())\n            result_e[None, 1].store(sReg[(None, tidx % 128), it * 2 + 1].load())\n            sD[(tidx % 128, (None, it % 2)), 0, sub_widx * 2 + it // 2, 0].store(\n                result_e[None].load().to(self.q_dtype)\n            )\n\n    @cute.jit\n    def __call__(\n        self,\n        q_iter: cute.Pointer,\n        k_iter: cute.Pointer,\n        v_iter: cute.Pointer,\n        o_iter: cute.Pointer,\n        g_iter: cute.Pointer,\n        beta_iter: cute.Pointer,\n        problem_size: Tuple[\n            cutlass.Int32,\n            cutlass.Int32,\n            cutlass.Int32,\n            cutlass.Int32,\n            cutlass.Int32,\n            cutlass.Int32,\n        ],\n        initial_state_f32_iter: Optional[cute.Pointer],\n        state_output: Optional[cute.Pointer],\n        scale: Optional[float],\n        cum_seqlen_q: Optional[cute.Tensor] = None,\n        stream: cuda.CUstream = None,\n    ):\n        \"\"\"Host-side entry: build tensor layouts, TMA descriptors, smem storage, and launch the kernel.\"\"\"\n\n        b, s_q, s_sum, h_q, h_v, d = problem_size\n\n        h_r = h_v // h_q\n        o_offset = 0 if cum_seqlen_q is None else (-s_q * d * h_r * h_q)\n        b_qk = b if cum_seqlen_q is None else s_sum\n        b_o = b if cum_seqlen_q is None else s_q * (1 + b)\n        b_v = b if cum_seqlen_q is None else s_sum\n\n        stride_b_qk = h_q * s_q * d if cum_seqlen_q is None else d * h_q\n        stride_b_vo = h_r * h_q * s_q * d if cum_seqlen_q is None else d * h_q * h_r\n\n        b_gb = b if cum_seqlen_q is None else 1\n        stride_b_gb = h_r * h_q * s_sum if cum_seqlen_q is None else 0\n        q_layout = cute.make_layout(\n            (s_sum, d, ((h_r, h_q), b_qk)),\n            stride=(d * h_q, 1, ((0, d), stride_b_qk)),\n        )\n        q = cute.make_tensor(q_iter, q_layout)\n\n        k_layout = cute.make_layout(\n            (s_sum, d, ((h_r, h_q), b_qk)),\n            stride=(d * h_q, 1, ((0, d), stride_b_qk)),\n        )\n        k = cute.make_tensor(k_iter, k_layout)\n        v_layout = cute.make_layout(\n            (d, s_sum, ((h_r, h_q), b_v)),\n            stride=(1, d * h_q * h_r, ((d, d * h_r), stride_b_vo)),\n        )\n        v = cute.make_tensor(v_iter, v_layout)\n        o_layout = cute.make_layout(\n            (s_q, d, ((h_r, h_q), b_o)),\n            stride=(d * h_r * h_q, 1, ((d, d * h_r), stride_b_vo)),\n        )\n        o = cute.make_tensor(o_iter + o_offset, o_layout)\n\n        state_layout = cute.make_layout(\n            (self.head_dim, self.head_dim, ((h_r, h_q), b)),\n            stride=(\n                self.head_dim,\n                1,\n                (\n                    (\n                        self.head_dim * self.head_dim,\n                        h_r * self.head_dim * self.head_dim,\n                    ),\n                    h_q * h_r * self.head_dim * self.head_dim,\n                ),\n            ),\n        )\n\n        state_input_f32 = (\n            None\n            if cutlass.const_expr(initial_state_f32_iter is None)\n            else cute.make_tensor(initial_state_f32_iter, state_layout)\n        )\n        state_output = (\n            None\n            if cutlass.const_expr(state_output is None)\n            else cute.make_tensor(state_output, state_layout)\n        )\n\n        gb_layout = cute.make_layout(\n            (s_sum, 1, ((h_r, h_q), b_gb)),\n            stride=(h_r * h_q, 0, ((1, h_r), stride_b_gb)),\n        )\n        gate = cute.make_tensor(g_iter, gb_layout)\n        beta = cute.make_tensor(beta_iter, gb_layout)\n\n        if cutlass.const_expr(scale is None):\n            scale = 1.0 / cute.math.sqrt(cutlass.Float32(d))\n\n        # setup static attributes before smem/grid/tma computation\n        self.q_dtype = q.element_type\n        self.k_dtype = k.element_type\n        self.v_dtype = v.element_type\n        self.o_dtype = o.element_type\n        self.g_dtype = gate.element_type\n        self.beta_dtype = beta.element_type\n\n        self.i_dtype = self.q_dtype\n\n        self.tile_sched_params, grid = self._compute_grid(\n            cute.shape((s_q, d, ((h_r, h_q), b))),\n            self.cta_tiler,\n            self.is_persistent,\n        )\n\n        self.q_major_mode = utils.LayoutEnum.from_tensor(q).mma_major_mode()\n        self.k_major_mode = utils.LayoutEnum.from_tensor(k).mma_major_mode()\n        self.v_major_mode = utils.LayoutEnum.from_tensor(v).mma_major_mode()\n        self.o_layout = utils.LayoutEnum.from_tensor(o)\n        self.s_output = utils.LayoutEnum.ROW_MAJOR\n\n        cta_group = tcgen05.CtaGroup.ONE\n\n        qk_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.q_dtype,\n            self.q_major_mode,\n            self.k_major_mode,\n            self.acc_dtype,\n            cta_group,\n            self.qk_mma_tiler[:2],\n        )\n\n        update_s_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            tcgen05.OperandMajorMode.MN,\n            tcgen05.OperandMajorMode.MN,\n            self.acc_dtype,\n            cta_group,\n            self.update_s_mma_tiler[:2],\n        )\n\n        o_intra_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            tcgen05.OperandMajorMode.K,\n            tcgen05.OperandMajorMode.MN,\n            self.acc_dtype,\n            cta_group,\n            self.o_intra_mma_tiler[:2],\n        )\n\n        o_intra_tiled_ts_mma_new = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            tcgen05.OperandMajorMode.K,\n            tcgen05.OperandMajorMode.MN,\n            self.acc_dtype,\n            cta_group,\n            self.o_intra_mma_tiler[:2],\n            tcgen05.OperandSource.TMEM,\n        )\n\n        qs_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            tcgen05.OperandMajorMode.K,\n            tcgen05.OperandMajorMode.K,\n            self.acc_dtype,\n            cta_group,\n            self.qs_mma_tiler[:2],\n            tcgen05.OperandSource.TMEM,\n        )\n\n        kkt_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.k_dtype,\n            self.k_major_mode,\n            self.k_major_mode,\n            self.acc_dtype,\n            cta_group,\n            self.kkt_mma_tiler[:2],\n        )\n\n        kst_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.i_dtype,\n            self.k_major_mode,\n            self.k_major_mode,\n            self.acc_dtype,\n            cta_group,\n            self.kst_mma_tiler[:2],\n        )\n\n        invert_sub_tiled_mma_ss_l0 = sm100_utils.make_trivial_tiled_mma(\n            self.invert_type_ab,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.invert_acc_type,\n            cta_group,\n            self.invert_mma_sub_l0_tiler[:2],\n        )\n        invert_sub_tiled_mma_ts_l0 = sm100_utils.make_trivial_tiled_mma(\n            self.invert_type_ab,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.invert_acc_type,\n            cta_group,\n            self.invert_mma_sub_l0_tiler[:2],\n            tcgen05.OperandSource.TMEM,\n        )\n\n        invert_sub_tiled_mma_ss_l1 = sm100_utils.make_trivial_tiled_mma(\n            self.invert_type_ab,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.invert_acc_type,\n            cta_group,\n            self.invert_mma_sub_l1_tiler[:2],\n        )\n        invert_sub_tiled_mma_ts_l1 = sm100_utils.make_trivial_tiled_mma(\n            self.invert_type_ab,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.invert_acc_type,\n            cta_group,\n            self.invert_mma_sub_l1_tiler[:2],\n            tcgen05.OperandSource.TMEM,\n        )\n\n        tuw_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.k_dtype,\n            self.k_major_mode,\n            tcgen05.OperandMajorMode.MN,\n            self.acc_dtype,\n            cta_group,\n            self.tuw_mma_tiler[:2],\n        )\n\n        self.cluster_layout_vmnk = cute.tiled_divide(\n            cute.make_layout(self.cluster_shape_mnk),\n            (qk_tiled_mma.thr_id.shape,),\n        )\n\n        q_smem_layout_staged = sm100_utils.make_smem_layout_a(\n            qk_tiled_mma,\n            self.qk_mma_tiler,\n            self.q_dtype,\n            self.q_stage,\n        )\n        k_smem_layout_staged = sm100_utils.make_smem_layout_b(\n            qk_tiled_mma,\n            self.qk_mma_tiler,\n            self.k_dtype,\n            self.kv_stage,\n        )\n\n        qk_smem_layout_staged = sm100_utils.make_smem_layout_b(\n            qk_tiled_mma,\n            self.qk_mma_tiler,\n            self.i_dtype,\n            self.qk_stage,\n        )\n\n        state_smem_layout_staged = sm100_utils.make_smem_layout_b(\n            kst_tiled_mma,\n            self.kst_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n        )\n\n        o_intra_smem_layout_staged_a = make_smem_layout_a_kind(\n            o_intra_tiled_mma,\n            self.o_intra_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        o_intra_smem_layout_staged_b = make_smem_layout_b_kind(\n            o_intra_tiled_mma,\n            self.o_intra_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        o_intra_smem_layout_staged_a_new = make_smem_layout_a_kind(\n            o_intra_tiled_ts_mma_new,\n            self.o_intra_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        qs_smem_layout_staged_a = sm100_utils.make_smem_layout_a(\n            qs_tiled_mma,\n            self.qs_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n        )\n\n        qs_smem_layout_staged_b = sm100_utils.make_smem_layout_b(\n            qs_tiled_mma,\n            self.qs_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n        )\n\n        update_s_smem_layout_staged_a = make_smem_layout_a_kind(\n            update_s_tiled_mma,\n            self.update_s_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        update_s_smem_layout_staged_b = make_smem_layout_b_kind(\n            update_s_tiled_mma,\n            self.update_s_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        state_output_smem_layout_staged = make_smem_layout_epi_kind(\n            self.state_dtype,\n            self.s_output,\n            self.state_output_tiler,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        o_output_smem_layout_staged = make_smem_layout_epi_kind(\n            self.i_dtype,\n            self.o_layout,\n            self.o_output_tiler,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        ivt_smem_layout = cute.make_layout(\n            ((36, 32), 4)\n        )  # padding, remove smem bank conflict\n        # ivt_smem_layout = cute.make_layout(((32, 32), 4))  # padding, remove smem bank conflict\n\n        sub_inner_smem_layout_staged = make_smem_layout_a_kind(\n            invert_sub_tiled_mma_ss_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.sub_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        invert_sub_smem_layout_staged_ss_l0_a = sm100_utils.make_smem_layout_a(\n            invert_sub_tiled_mma_ss_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ss_l0_b = sm100_utils.make_smem_layout_b(\n            invert_sub_tiled_mma_ss_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ts_l0_a = sm100_utils.make_smem_layout_a(\n            invert_sub_tiled_mma_ts_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ts_l0_b = sm100_utils.make_smem_layout_b(\n            invert_sub_tiled_mma_ts_l0,\n            self.invert_mma_sub_l0_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ss_l1_a = sm100_utils.make_smem_layout_a(\n            invert_sub_tiled_mma_ss_l1,\n            self.invert_mma_sub_l1_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ss_l1_b = sm100_utils.make_smem_layout_b(\n            invert_sub_tiled_mma_ss_l1,\n            self.invert_mma_sub_l1_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ts_l1_a = sm100_utils.make_smem_layout_a(\n            invert_sub_tiled_mma_ts_l1,\n            self.invert_mma_sub_l1_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        invert_sub_smem_layout_staged_ts_l1_b = sm100_utils.make_smem_layout_b(\n            invert_sub_tiled_mma_ts_l1,\n            self.invert_mma_sub_l1_tiler,\n            self.invert_type_ab,\n            self.invert_sub_stage,\n        )\n\n        # tuw\n        tuw_smem_layout_staged_a = make_smem_layout_a_kind(\n            tuw_tiled_mma,\n            self.tuw_mma_tiler,\n            self.q_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.K_INTER,\n        )\n\n        tuw_smem_layout_staged_b = make_smem_layout_b_kind(\n            tuw_tiled_mma,\n            self.tuw_mma_tiler,\n            self.q_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        v_smem_layout_staged_b = make_smem_layout_b_kind(\n            tuw_tiled_mma,\n            self.tuw_mma_tiler,\n            self.i_dtype,\n            self.one_stage,\n            cute.nvgpu.tcgen05.SmemLayoutAtomKind.MN_INTER,\n        )\n\n        # TMA\n        tma_load_op = cute.nvgpu.cpasync.CopyBulkTensorTileG2SOp(cta_group)\n        tma_store_op = cute.nvgpu.cpasync.CopyBulkTensorTileS2GOp()\n\n        # TMA load for Q\n        q_smem_layout = cute.select(q_smem_layout_staged, mode=[0, 1, 2])\n        tma_atom_q, tma_tensor_q = cute.nvgpu.make_tiled_tma_atom_A(\n            tma_load_op,\n            q,\n            q_smem_layout,\n            self.qk_mma_tiler,\n            qk_tiled_mma,\n            self.cluster_layout_vmnk.shape,\n        )\n\n        # TMA load for K\n        k_smem_layout = cute.select(k_smem_layout_staged, mode=[0, 1, 2])\n        tma_atom_k, tma_tensor_k = cute.nvgpu.make_tiled_tma_atom_B(\n            tma_load_op,\n            k,\n            k_smem_layout,\n            self.qk_mma_tiler,\n            qk_tiled_mma,\n            self.cluster_layout_vmnk.shape,\n        )\n\n        # TMA load for V\n        v_smem_layout = cute.select(v_smem_layout_staged_b, mode=[0, 1, 2])\n        tma_atom_v, tma_tensor_v = cute.nvgpu.make_tiled_tma_atom_B(\n            tma_load_op,\n            v,\n            v_smem_layout,\n            self.tuw_mma_tiler,\n            tuw_tiled_mma,\n            self.cluster_layout_vmnk.shape,\n        )\n\n        fake_state_tiled_mma = sm100_utils.make_trivial_tiled_mma(\n            self.state_dtype,\n            self.q_major_mode,\n            self.k_major_mode,\n            self.state_dtype,\n            cta_group,\n            self.qk_mma_tiler[:2],\n        )\n        state_smem_layout_f32_staged = sm100_utils.make_smem_layout_b(\n            fake_state_tiled_mma,\n            self.qk_mma_tiler,\n            self.state_dtype,\n            self.one_stage,\n        )\n        state_smem_layout_f32 = cute.select(\n            state_smem_layout_f32_staged, mode=[0, 1, 2]\n        )\n        tma_atom_state_f32, tma_tensor_state_f32 = (\n            cute.nvgpu.make_tiled_tma_atom_B(\n                tma_load_op,\n                state_input_f32,\n                state_smem_layout_f32,\n                self.qk_mma_tiler,\n                fake_state_tiled_mma,\n                self.cluster_layout_vmnk.shape,\n            )\n            if cutlass.const_expr(state_input_f32 is not None)\n            else (None, None)\n        )\n\n        state_smem_layout_output = cute.select(\n            state_output_smem_layout_staged, mode=[0, 1]\n        )\n        tma_atom_state_output, tma_tensor_state_output = (\n            cutlass.cute.nvgpu.cpasync.make_tiled_tma_atom(\n                tma_store_op,\n                state_output,\n                state_smem_layout_output,\n                cute.composition(\n                    cute.make_identity_layout(state_output.shape),\n                    self.state_output_tiler,\n                ),\n            )\n            if cutlass.const_expr(state_output is not None)\n            else (None, None)\n        )\n\n        o_cta_v_layout = cute.composition(\n            cute.make_identity_layout(o.shape), self.o_output_tiler\n        )\n        o_smem_layout_output = cute.select(o_output_smem_layout_staged, mode=[0, 1])\n        tma_atom_o_output, tma_tensor_o_output = (\n            cutlass.cute.nvgpu.cpasync.make_tiled_tma_atom(\n                tma_store_op,\n                o,\n                o_smem_layout_output,\n                o_cta_v_layout,\n            )\n        )\n\n        gate_smem_layout_staged = cute.make_layout(\n            (self.chunk_size, 1, self.gate_stage)\n        )\n        gate_smem_layout = cute.select(gate_smem_layout_staged, mode=[0, 1])\n\n        beta_smem_layout_staged = cute.make_layout(\n            (self.chunk_size, 1, self.beta_stage)\n        )\n        beta_smem_layout = cute.select(beta_smem_layout_staged, mode=[0, 1])\n\n        q_copy_size = cute.size_in_bytes(self.q_dtype, q_smem_layout)\n        k_copy_size = cute.size_in_bytes(self.k_dtype, k_smem_layout)\n        v_copy_size = cute.size_in_bytes(self.v_dtype, v_smem_layout)\n        state_copy_size = cute.size_in_bytes(self.i_dtype, state_smem_layout_f32)\n        state_f32_copy_size = cute.size_in_bytes(\n            self.state_dtype, state_smem_layout_f32\n        )\n        gate_copy_size = cute.size_in_bytes(self.g_dtype, gate_smem_layout)\n        beta_copy_size = cute.size_in_bytes(self.beta_dtype, beta_smem_layout)\n        self.tma_copy_q_bytes = q_copy_size\n        self.tma_copy_kv_bytes = k_copy_size\n        self.tma_copy_v_bytes = v_copy_size\n        self.tma_copy_state_bytes = state_copy_size\n        self.tma_copy_state_f32_bytes = state_f32_copy_size\n        self.tma_copy_gate_bytes = gate_copy_size\n        self.tma_copy_beta_bytes = beta_copy_size\n\n        # Shared memory storage\n        @cute.struct\n        class SharedStorage:\n            load_qk_mbar_ptr: cute.struct.MemRange[Int64, self.qk_stage * 2]\n            load_v_mbar_ptr: cute.struct.MemRange[Int64, self.one_stage * 2]\n            load_state_mbar_ptr: cute.struct.MemRange[Int64, self.one_stage * 2]\n            mma_cudacore_mbar_ptr0: cute.struct.MemRange[Int64, 2]\n            mma_qk_mbar_ptr0: cute.struct.MemRange[Int64, self.mma_qk_stage * 2]\n\n            w0_epi_mbar_ptr: cute.struct.MemRange[Int64, 2]\n            epi_w0_mbar_ptr: cute.struct.MemRange[Int64, 2]\n            gb_w0_mbar_ptr: cute.struct.MemRange[Int64, self.gate_stage * 2]\n\n            tmem_dealloc_mbar_ptr: cute.struct.MemRange[Int64, 1]\n            # Tmem holding buffer\n            tmem_holding_buf: Int32\n\n            sV: cute.struct.Align[\n                cute.struct.MemRange[self.i_dtype, cute.cosize(v_smem_layout_staged_b)],\n                self.buffer_align_bytes,\n            ]\n\n            sQK: cute.struct.Align[\n                cute.struct.MemRange[self.q_dtype, cute.cosize(qk_smem_layout_staged)],\n                self.buffer_align_bytes,\n            ]\n\n            sIvt: cute.struct.Align[\n                cute.struct.MemRange[self.acc_dtype, cute.cosize(ivt_smem_layout)],\n                self.buffer_align_bytes,\n            ]\n\n            sGate: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.g_beta_dtype, cute.cosize(gate_smem_layout_staged)\n                ],\n                self.buffer_align_bytes,\n            ]\n            sGateCumsum: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.g_beta_dtype,\n                    cute.cosize(cute.select(gate_smem_layout_staged, mode=[0, 1])),\n                ],\n                self.buffer_align_bytes,\n            ]\n            sBeta: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.g_beta_dtype, cute.cosize(beta_smem_layout_staged)\n                ],\n                self.buffer_align_bytes,\n            ]\n            sSubInner: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.invert_type_ab, cute.cosize(sub_inner_smem_layout_staged)\n                ],\n                self.buffer_align_bytes,\n            ]\n\n            sState: cute.struct.Align[\n                cute.struct.MemRange[\n                    self.i_dtype, cute.cosize(state_smem_layout_staged)\n                ],\n                self.buffer_align_bytes,\n            ]\n\n        self.shared_storage = SharedStorage\n\n        if cutlass.const_expr(stream is None):\n            stream = cutlass.cuda.default_stream()\n\n        # Launch kernel\n        self.kernel(\n            qk_tiled_mma,\n            o_intra_tiled_mma,\n            o_intra_tiled_ts_mma_new,\n            qs_tiled_mma,\n            update_s_tiled_mma,\n            kkt_tiled_mma,\n            kst_tiled_mma,\n            fake_state_tiled_mma,\n            invert_sub_tiled_mma_ss_l0,\n            invert_sub_tiled_mma_ts_l0,\n            invert_sub_tiled_mma_ss_l1,\n            invert_sub_tiled_mma_ts_l1,\n            tuw_tiled_mma,\n            tma_atom_q,\n            tma_tensor_q,\n            tma_atom_k,\n            tma_tensor_k,\n            tma_atom_v,\n            tma_tensor_v,\n            tma_atom_state_f32,\n            tma_tensor_state_f32,\n            gate,\n            beta,\n            o,\n            tma_atom_state_output,\n            tma_tensor_state_output,\n            tma_atom_o_output,\n            tma_tensor_o_output,\n            cum_seqlen_q,\n            q_smem_layout_staged,\n            k_smem_layout_staged,\n            qk_smem_layout_staged,\n            o_intra_smem_layout_staged_a,\n            o_intra_smem_layout_staged_b,\n            o_intra_smem_layout_staged_a_new,\n            qs_smem_layout_staged_a,\n            qs_smem_layout_staged_b,\n            update_s_smem_layout_staged_a,\n            update_s_smem_layout_staged_b,\n            state_smem_layout_staged,\n            state_smem_layout_f32_staged,\n            state_output_smem_layout_staged,\n            o_output_smem_layout_staged,\n            gate_smem_layout_staged,\n            beta_smem_layout_staged,\n            ivt_smem_layout,\n            sub_inner_smem_layout_staged,\n            invert_sub_smem_layout_staged_ss_l0_a,\n            invert_sub_smem_layout_staged_ss_l0_b,\n            invert_sub_smem_layout_staged_ts_l0_a,\n            invert_sub_smem_layout_staged_ts_l0_b,\n            invert_sub_smem_layout_staged_ss_l1_a,\n            invert_sub_smem_layout_staged_ss_l1_b,\n            invert_sub_smem_layout_staged_ts_l1_a,\n            invert_sub_smem_layout_staged_ts_l1_b,\n            tuw_smem_layout_staged_a,\n            tuw_smem_layout_staged_b,\n            v_smem_layout_staged_b,\n            scale,\n            self.tile_sched_params,\n        ).launch(\n            grid=grid,\n            block=[self.threads_per_cta, 1, 1],\n            cluster=self.cluster_shape_mnk,\n            stream=stream,\n            min_blocks_per_mp=1,\n        )\n\n    @staticmethod\n    def _compute_grid(\n        o_shape: cute.Shape,\n        cta_tiler: Tuple[int, int, int],\n        is_persistent: bool,\n    ) -> Tuple[GdnStaticTileSchedulerParams, Tuple[int, int, int]]:\n        tile_sched_params = create_gdn_static_tile_scheduler_params(\n            is_persistent,\n            (\n                cute.ceil_div(cute.size(o_shape[1]), cta_tiler[2]),\n                cute.size(o_shape[2][0]),\n                cute.size(o_shape[2][1]),\n            ),\n        )\n        grid = GdnStaticTileScheduler.get_grid_shape(tile_sched_params)\n        return tile_sched_params, grid\n\n\n# ============================================================================\n# FlashInfer API Layer\n# ============================================================================\n\n\n@functools.lru_cache(maxsize=128)\ndef _get_problem_size(q_shape, v_shape, cu_seqlens_tuple):\n    \"\"\"Compute problem_size, cached by (q_shape, v_shape, cu_seqlens tuple).\n\n    Args:\n        q_shape: Tuple of (b, s_q, h_q, d).\n        v_shape: Tuple of (b, s_v, h_v, d).\n        cu_seqlens_tuple: Tuple of cumulative sequence lengths, or None.\n    \"\"\"\n    b, s_q, h_q, d = q_shape\n    _, _, h_v, _ = v_shape\n    max_s_q = s_q\n    sum_s_q = s_q\n    if cu_seqlens_tuple is not None:\n        sum_s_q = cu_seqlens_tuple[-1]\n        b = len(cu_seqlens_tuple) - 1\n        max_s_q = max(cu_seqlens_tuple[i + 1] - cu_seqlens_tuple[i] for i in range(b))\n        return (b, max_s_q, sum_s_q, h_q, h_v, d)\n    return (b, max_s_q, sum_s_q, h_q, h_v, d)\n\n\n@functools.cache\ndef _get_compiled_gdn_prefill_kernel(\n    problem_size,\n    dtype: torch.dtype,\n    is_varlen: bool,\n    is_initial_state: bool,\n    is_output_state: bool,\n    scale: float,\n):\n    \"\"\"Cache compiled kernel for given configuration.\"\"\"\n    return {}\n\n\ndef chunk_gated_delta_rule(\n    q: torch.Tensor,\n    k: torch.Tensor,\n    v: torch.Tensor,\n    g: torch.Tensor,\n    beta: torch.Tensor,\n    scale: Optional[float] = None,\n    initial_state: Optional[torch.Tensor] = None,\n    output_final_state: bool = False,\n    cu_seqlens: Optional[torch.Tensor] = None,\n    use_qk_l2norm_in_kernel: bool = False,\n    output: Optional[torch.Tensor] = None,\n    output_state: Optional[torch.Tensor] = None,\n) -> Union[torch.Tensor, Tuple[torch.Tensor, torch.Tensor]]:\n    \"\"\"Public API: compile (on first call) and run the GDN chunked linear attention kernel.\n\n    Args:\n        q, k: (B, T, H_qk, D) query and key tensors (f16/bf16).\n        v:     (B, T, H_v, D) value tensor (f16/bf16). H_v must be a multiple of H_qk.\n        g:     (1, total_seq_len, H_v) gate values (f32, log-space).\n        beta:  (1, total_seq_len, H_v) beta values (f32, sigmoid-space).\n        scale: Scale factor for the attention scores. Defaults to 1/sqrt(D).\n        initial_state: (B, H_v, D, D) recurrent state (f32), or None for zero init.\n        output_final_state: If True, return the final state alongside output.\n        cu_seqlens: Cumulative sequence lengths for variable-length batching.\n        use_qk_l2norm_in_kernel: If True, use L2 norm of QK in the kernel.(Not supported yet)\n        output: Pre-allocated output tensor, or None to allocate internally.\n        output_state: Pre-allocated state output tensor, or None.\n\n    Returns:\n        output or (output, output_state) depending on output_final_state.\n    \"\"\"\n\n    # Allocate output if needed\n    if output is None:\n        output = torch.empty_like(v)\n\n    # Check if supported\n    if not GDN.can_implement(\n        tuple(q.shape),\n        tuple(v.shape),\n        q.dtype,\n        output.dtype,\n        beta.dtype,\n        use_qk_l2norm_in_kernel,\n    ):\n        raise ValueError(\"Unsupported input shape or dtype\")\n    cu_seqlens_tuple = tuple(cu_seqlens.tolist()) if cu_seqlens is not None else None\n    problem_size = _get_problem_size(tuple(q.shape), tuple(v.shape), cu_seqlens_tuple)\n\n    # Allocate output_state if needed, current alloc both case.\n    # TODO: Remove output_state when output_final_state is false.\n    if output_state is None:\n        output_state = torch.empty(\n            (problem_size[0], problem_size[4], problem_size[5], problem_size[5]),\n            dtype=torch.float32,\n            device=q.device,\n        )\n\n    # Compile kernel with TVM FFI (cached)\n    is_varlen = cu_seqlens is not None\n    is_initial_state = initial_state is not None\n    is_output_state = output_state is not None\n    cache_key = (\n        problem_size,\n        q.dtype,\n        is_varlen,\n        is_initial_state,\n        is_output_state,\n        scale,\n    )\n    cache = _get_compiled_gdn_prefill_kernel(*cache_key)\n\n    current_stream = cuda.CUstream(torch.cuda.current_stream().cuda_stream)\n\n    if \"compiled_gdn\" not in cache:\n        # GDN kernel\n        gdn = GDN()\n        q_tensor = from_dlpack(q, assumed_align=16, enable_tvm_ffi=True)\n        k_tensor = from_dlpack(k, assumed_align=16, enable_tvm_ffi=True)\n        v_tensor = from_dlpack(v, assumed_align=16, enable_tvm_ffi=True)\n        o_tensor = from_dlpack(output, assumed_align=16, enable_tvm_ffi=True)\n        gate_tensor = from_dlpack(g, assumed_align=16, enable_tvm_ffi=True)\n        beta_tensor = from_dlpack(beta, assumed_align=16, enable_tvm_ffi=True)\n        cu_seqlens_tensor = (\n            from_dlpack(cu_seqlens, assumed_align=16, enable_tvm_ffi=True)\n            if cu_seqlens is not None\n            else None\n        )\n        state_tensor = (\n            from_dlpack(initial_state, assumed_align=16, enable_tvm_ffi=True)\n            if initial_state is not None\n            else None\n        )\n        state_output_tensor = (\n            from_dlpack(output_state, assumed_align=16, enable_tvm_ffi=True)\n            if output_state is not None\n            else None\n        )\n\n        # Compile GDN kernel\n        options = EnableTVMFFI\n        compiled_gdn = cute.compile[options](\n            gdn,\n            q_tensor.iterator,\n            k_tensor.iterator,\n            v_tensor.iterator,\n            o_tensor.iterator,\n            gate_tensor.iterator,\n            beta_tensor.iterator,\n            problem_size,\n            state_tensor.iterator if state_tensor is not None else None,\n            state_output_tensor.iterator if state_output_tensor is not None else None,\n            scale,\n            cu_seqlens_tensor,\n            stream=current_stream,\n        )\n        cache[\"compiled_gdn\"] = compiled_gdn\n\n    compiled_gdn = cache[\"compiled_gdn\"]\n\n    # Run GDN kernel\n    compiled_gdn(\n        q.data_ptr(),\n        k.data_ptr(),\n        v.data_ptr(),\n        output.data_ptr(),\n        g.data_ptr(),\n        beta.data_ptr(),\n        problem_size,\n        initial_state.data_ptr() if initial_state is not None else None,\n        output_state.data_ptr() if output_state is not None else None,\n        scale,\n        cu_seqlens,\n        stream=current_stream,\n    )\n\n    if output_final_state:\n        return output, output_state\n    else:\n        return output\n"
+    },
+    {
+      "path": "gdn_blackwell/gdn_helpers.py",
+      "content": "\"\"\"\nCopyright (c) 2026 by FlashInfer team.\n\nLicensed under the Apache License, Version 2.0 (the \"License\");\nyou may not use this file except in compliance with the License.\nYou may obtain a copy of the License at\n\n  http://www.apache.org/licenses/LICENSE-2.0\n\nUnless required by applicable law or agreed to in writing, software\ndistributed under the License is distributed on an \"AS IS\" BASIS,\nWITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\nSee the License for the specific language governing permissions and\nlimitations under the License.\n\"\"\"\n\nfrom typing import Type, Union\n\nimport cutlass\nimport cutlass.cute as cute\n\n\ndef make_smem_layout_a_kind(\n    tiled_mma: cute.TiledMma,\n    mma_tiler_mnk: cute.Tile,\n    a_dtype: Type[cutlass.Numeric],\n    num_stages: int,\n    kind: cute.nvgpu.tcgen05.SmemLayoutAtomKind,\n    *,\n    loc=None,\n    ip=None,\n) -> Union[cute.Layout, cute.ComposedLayout]:\n    \"\"\"This function helps with:\n    1. Get the partitioned shape of the A tensor based on the tiled_mma & MMA tiler.\n    2. Select the heuristic SMEM layout atom based on the A tensor's majorness, the data type, and the major mode size.\n    3. cute.Tile the SMEM layout atom to the MMA tile shape.\n    4. Stage the SMEM layout based on the number of stages.\n\n    :param tiled_mma: The tiled MMA used to partition tensor A\n    :type tiled_mma: cute.TiledMma\n    :param mma_tiler_mnk: The MMA tile shape\n    :type mma_tiler_mnk: cute.cute.Tile\n    :param a_dtype: The element type for tensor A\n    :type a_dtype: Type[Numeric]\n    :param num_stages: The number of pipeline stages for tensor A\n    :type num_stages: int\n    :param kind:         The kind of layout Atom\n    :type kind:          SmemLayoutAtomKind\n\n    :return: SMEM layout for tensor A\n    :rtype: Union[cute.Layout, cute.ComposedLayout]\n    \"\"\"\n\n    is_k_major = (\n        tiled_mma.op.a_major_mode == cutlass.cute.nvgpu.tcgen05.OperandMajorMode.K\n    )\n    a_smem_shape = tiled_mma.partition_shape_A(\n        cute.dice(mma_tiler_mnk, (1, None, 1), loc=loc, ip=ip)\n    )\n    a_smem_layout_atom = cute.nvgpu.tcgen05.make_smem_layout_atom(\n        kind,\n        a_dtype,\n        loc=loc,\n        ip=ip,\n    )\n    a_smem_layout_staged = cute.nvgpu.tcgen05.tile_to_mma_shape(\n        a_smem_layout_atom,\n        cute.append(a_smem_shape, num_stages, loc=loc, ip=ip),\n        order=((1, 0, 2) if not is_k_major else (0, 1, 2)),\n        loc=loc,\n        ip=ip,\n    )\n    return a_smem_layout_staged\n\n\ndef make_smem_layout_b_kind(\n    tiled_mma: cute.TiledMma,\n    mma_tiler_mnk: cute.Tile,\n    b_dtype: Type[cutlass.Numeric],\n    num_stages: int,\n    kind: cute.nvgpu.tcgen05.SmemLayoutAtomKind,\n    *,\n    loc=None,\n    ip=None,\n) -> Union[cute.Layout, cute.ComposedLayout]:\n    \"\"\"This function helps:\n    1. Get the partitioned shape of the B tensor based on the tiled_mma & MMA tiler.\n    2. Select the heuristic SMEM layout atom based on the B tensor's majorness, the data type, and the major mode size.\n    3. cute.Tile the SMEM layout atom to the MMA tile shape.\n    4. Stage the SMEM layout based on the number of stages.\n\n    :param tiled_mma: The tiled MMA which is used to partition the B tensor.\n    :type tiled_mma: cute.TiledMma\n    :param mma_tiler_mnk: The MMA tile shape.\n    :type mma_tiler_mnk: cute.cute.Tile\n    :param b_dtype: The element type for the B tensor.\n    :type b_dtype: Type[Numeric]\n    :param num_stages: The stage of the B tensor.\n    :type num_stages: int\n    :param kind:         The kind of layout Atom\n    :type kind:          SmemLayoutAtomKind\n\n    :return: SMEM layout for the B tensor.\n    :rtype: Union[cute.Layout, cute.ComposedLayout]\n    \"\"\"\n\n    is_k_major = (\n        tiled_mma.op.b_major_mode == cutlass.cute.nvgpu.tcgen05.OperandMajorMode.K\n    )\n    b_smem_shape = tiled_mma.partition_shape_B(\n        cute.dice(mma_tiler_mnk, (None, 1, 1), loc=loc, ip=ip)\n    )\n    b_smem_layout_atom = cute.nvgpu.tcgen05.make_smem_layout_atom(\n        kind,\n        b_dtype,\n        loc=loc,\n        ip=ip,\n    )\n    b_smem_layout_staged = cute.nvgpu.tcgen05.tile_to_mma_shape(\n        b_smem_layout_atom,\n        cute.append(b_smem_shape, num_stages, loc=loc, ip=ip),\n        order=((1, 0, 2) if not is_k_major else (0, 1, 2)),\n        loc=loc,\n        ip=ip,\n    )\n\n    return b_smem_layout_staged\n\n\ndef make_smem_layout_epi_kind(\n    epi_dtype: Type[cutlass.Numeric],\n    epi_layout: cutlass.utils.LayoutEnum,\n    epi_tile: cute.Tile,\n    epi_stage: int,\n    kind: cute.nvgpu.tcgen05.SmemLayoutAtomKind,\n    *,\n    loc=None,\n    ip=None,\n) -> Union[cute.Layout, cute.ComposedLayout]:\n    \"\"\"This function helps:\n    1. Select the heuristic SMEM layout atom based on the epilog tile shape,\n       the epilog tensor's majorness, and the element type.\n    2. cute.Tile the SMEM layout atom to the epilog tile shape.\n    3. Stage the SMEM layout based on the number of stages.\n\n    :param epi_dtype: The element type for the epilog tensor.\n    :type epi_dtype: Type[Numeric]\n    :param epi_layout: The layout enum for the epilog tensor.\n    :type epi_layout: LayoutEnum\n    :param epi_tile: The epilogue tile shape.\n    :type epi_tile: cute.cute.Tile\n    :param epi_stage: The stage of the epilog tensor.\n    :type epi_stage: int\n\n    :return: SMEM layout for epilog tensors (usually C & D which are processed in the epilog)\n    :rtype: Union[cute.Layout, cute.ComposedLayout]\n    \"\"\"\n\n    epilog_shape = cute.product_each(\n        cute.shape(epi_tile, loc=loc, ip=ip), loc=loc, ip=ip\n    )\n\n    c_smem_layout_atom = cute.nvgpu.tcgen05.make_smem_layout_atom(\n        kind,\n        epi_dtype,\n        loc=loc,\n        ip=ip,\n    )\n    epi_smem_layout_staged = cute.tile_to_shape(\n        c_smem_layout_atom,\n        cute.append(epilog_shape, epi_stage, loc=loc, ip=ip),\n        order=((1, 0, 2) if not epi_layout.is_n_major_c() else (0, 1, 2)),\n        loc=loc,\n        ip=ip,\n    )\n\n    return epi_smem_layout_staged\n"
+    },
+    {
+      "path": "gdn_blackwell/gdn_tile_scheduler.py",
+      "content": "import cutlass\nimport cutlass.cute as cute\nimport cutlass.utils as utils\n\nfrom cutlass.cute.typing import Int32, Int64, Boolean\n\n\nclass GdnStaticTileSchedulerParams:\n    def __init__(\n        self,\n        is_persistent: bool,\n        problem_shape_mbh: cute.Shape,\n        *,\n        loc=None,\n        ip=None,\n    ):\n        self.is_persistent = is_persistent\n        self.problem_shape_mbh = problem_shape_mbh\n        self._loc = loc\n        self._ip = ip\n\n    def __extract_mlir_values__(self):\n        values, self._values_pos = [], []\n        for obj in [self.is_persistent, self.problem_shape_mbh]:\n            obj_values = cutlass.extract_mlir_values(obj)\n            values += obj_values\n            self._values_pos.append(len(obj_values))\n        return values\n\n    def __new_from_mlir_values__(self, values):\n        obj_list = []\n        for obj, n_items in zip(\n            [self.is_persistent, self.problem_shape_mbh], self._values_pos, strict=True\n        ):\n            obj_list.append(cutlass.new_from_mlir_values(obj, values[:n_items]))\n            values = values[n_items:]\n        return GdnStaticTileSchedulerParams(\n            *(tuple(obj_list)), loc=self._loc, ip=self._ip\n        )\n\n\ndef create_gdn_static_tile_scheduler_params(\n    is_persistent: bool,\n    problem_shape_mbh: cute.Shape,\n) -> GdnStaticTileSchedulerParams:\n    return GdnStaticTileSchedulerParams(is_persistent, problem_shape_mbh)\n\n\nclass GdnStaticTileScheduler:\n    def __init__(\n        self,\n        params: GdnStaticTileSchedulerParams,\n        current_work_linear_idx: Int32,\n        blk_coord: cute.Coord,\n        grid_shape: cute.Shape,\n        *,\n        loc=None,\n        ip=None,\n    ):\n        self._params = params\n        self._blk_coord = blk_coord\n        self._grid_shape = grid_shape\n        self._is_persistent = params.is_persistent\n        self._current_work_linear_idx = current_work_linear_idx\n        self._problem_shape_mbh = cute.make_layout(\n            params.problem_shape_mbh, loc=loc, ip=ip\n        )\n        self._num_blocks = cute.size(self._problem_shape_mbh, loc=loc, ip=ip)\n        self._is_first_block = True\n        self.num_persistent_sm = cute.size(grid_shape, loc=loc, ip=ip)\n        self._loc = loc\n        self._ip = ip\n\n    # called by host\n    @staticmethod\n    def get_grid_shape(\n        params: GdnStaticTileSchedulerParams,\n        *,\n        loc=None,\n        ip=None,\n    ) -> cute.Shape:\n        if params.is_persistent:\n            hardware_info = cutlass.utils.HardwareInfo()\n            sm_count = hardware_info.get_device_multiprocessor_count()\n            return (\n                cutlass.min(\n                    sm_count, cute.size(params.problem_shape_mbh, loc=loc, ip=ip)\n                ),\n                1,\n                1,\n            )\n        else:\n            return params.problem_shape_mbh\n\n    @staticmethod\n    def check_valid_work_for_seqlen_q(\n        q_tiler: int,\n        current_idx: Int32,\n        seqlen_q: Int32,\n    ) -> Boolean:\n        return current_idx * q_tiler < seqlen_q\n\n    def get_current_work(self, *, loc=None, ip=None) -> utils.WorkTileInfo:\n        is_valid = (\n            self._current_work_linear_idx < self._num_blocks\n            if self._is_persistent\n            else self._is_first_block\n        )\n\n        blk_coord = (0, 0, 0)\n        if self._is_persistent:\n            blk_coord = self._problem_shape_mbh.get_hier_coord(\n                self._current_work_linear_idx, loc=loc, ip=ip\n            )\n        else:\n            blk_coord = self._blk_coord\n\n        # cur_tile_coord is (mid, 0, (bid, hid))\n        cur_tile_coord = (\n            blk_coord[0],\n            0,\n            (blk_coord[1], blk_coord[2]),\n        )\n\n        return utils.WorkTileInfo(cur_tile_coord, is_valid)\n\n    def initial_work_tile_info(self, *, loc=None, ip=None):\n        return self.get_current_work(loc=loc, ip=ip)\n\n    def advance_to_next_work(self, *, advance_count=1, loc=None, ip=None):\n        if self._is_persistent:\n            self._current_work_linear_idx += advance_count * self.num_persistent_sm\n        self._is_first_block = False\n\n    def __extract_mlir_values__(self):\n        values = cutlass.extract_mlir_values(self._params)\n        values.extend(cutlass.extract_mlir_values(self._current_work_linear_idx))\n        values.extend(cutlass.extract_mlir_values(self._blk_coord))\n        values.extend(cutlass.extract_mlir_values(self._grid_shape))\n        return values\n\n    def __new_from_mlir_values__(self, values):\n        assert len(values) == 10\n        new_params = cutlass.new_from_mlir_values(self._params, values[0:3])\n        new_current_work_linear_idx = cutlass.new_from_mlir_values(\n            self._current_work_linear_idx, [values[3]]\n        )\n        new_blk_coord = cutlass.new_from_mlir_values(self._blk_coord, values[4:7])\n        new_grid_shape = cutlass.new_from_mlir_values(self._grid_shape, values[7:])\n        return GdnStaticTileScheduler(\n            new_params, new_current_work_linear_idx, new_blk_coord, new_grid_shape\n        )\n\n\ndef create_gdn_static_tile_scheduler(\n    params: GdnStaticTileSchedulerParams,\n    blk_coord: cute.Coord,\n    grid_shape: cute.Shape,\n) -> GdnStaticTileScheduler:\n    return GdnStaticTileScheduler(params, blk_coord[0], blk_coord, grid_shape)\n"
+    }
+  ],
+  "description": "Solution using FlashInfer SM100 CuTile chunk_gated_delta_rule for GDN prefill (qk4_v8_d128, k-last state layout) on NVIDIA B200 (Blackwell)."
+}
diff --git a/solutions/baseline/moe/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048/flashinfer_wrapper_9sdjf3.json b/solutions/baseline/moe/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048/flashinfer_wrapper_9sdjf3.json
new file mode 100644
index 0000000000000000000000000000000000000000..b0163c957078aad240c1498e091e99a3615eb492
--- /dev/null
+++ b/solutions/baseline/moe/moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048/flashinfer_wrapper_9sdjf3.json
@@ -0,0 +1,23 @@
+{
+  "name": "flashinfer_wrapper_9sdjf3",
+  "definition": "moe_fp8_block_scale_ds_routing_topk8_ng8_kg4_e32_h7168_i2048",
+  "author": "flashinfer",
+  "spec": {
+    "language": "python",
+    "target_hardware": [
+      "NVIDIA B200"
+    ],
+    "entry_point": "main.py::run",
+    "dependencies": [
+      "flashinfer"
+    ],
+    "destination_passing_style": false
+  },
+  "sources": [
+    {
+      "path": "main.py",
+      "content": "import torch\nfrom flashinfer.fused_moe import trtllm_fp8_block_scale_moe\n\n\nNUM_EXPERTS_GLOBAL = 256\nTOP_K = 8\nN_GROUP = 8\nTOPK_GROUP = 4\nHIDDEN_SIZE = 7168\nINTERMEDIATE_SIZE = 2048\nBLOCK_SIZE = 128\n\n\n@torch.no_grad()\ndef run(\n    routing_logits: torch.Tensor,\n    routing_bias: torch.Tensor,\n    hidden_states: torch.Tensor,\n    hidden_states_scale: torch.Tensor,\n    gemm1_weights: torch.Tensor,\n    gemm1_weights_scale: torch.Tensor,\n    gemm2_weights: torch.Tensor,\n    gemm2_weights_scale: torch.Tensor,\n    local_expert_offset: int,\n    routed_scaling_factor: float,\n):\n    seq_len, num_experts = routing_logits.shape\n    local_num_experts = gemm1_weights.shape[0]\n\n    assert num_experts == NUM_EXPERTS_GLOBAL\n    assert hidden_states.shape == (seq_len, HIDDEN_SIZE)\n    assert hidden_states_scale.shape == (HIDDEN_SIZE // BLOCK_SIZE, seq_len)\n    assert gemm1_weights.shape == (local_num_experts, 2 * INTERMEDIATE_SIZE, HIDDEN_SIZE)\n    assert gemm1_weights_scale.shape == (\n        local_num_experts,\n        (2 * INTERMEDIATE_SIZE) // BLOCK_SIZE,\n        HIDDEN_SIZE // BLOCK_SIZE,\n    )\n    assert gemm2_weights.shape == (local_num_experts, HIDDEN_SIZE, INTERMEDIATE_SIZE)\n    assert gemm2_weights_scale.shape == (\n        local_num_experts,\n        HIDDEN_SIZE // BLOCK_SIZE,\n        INTERMEDIATE_SIZE // BLOCK_SIZE,\n    )\n    assert routing_bias is None or routing_bias.shape[-1] == NUM_EXPERTS_GLOBAL\n\n    if isinstance(local_expert_offset, torch.Tensor):\n        local_expert_offset = int(local_expert_offset.item())\n    else:\n        local_expert_offset = int(local_expert_offset)\n\n    if isinstance(routed_scaling_factor, torch.Tensor):\n        routed_scaling_factor = float(routed_scaling_factor.item())\n    else:\n        routed_scaling_factor = float(routed_scaling_factor)\n\n    routing_logits_f32 = routing_logits.to(torch.float32).contiguous()\n    hidden_states_scale_f32 = hidden_states_scale.to(torch.float32).contiguous()\n    gemm1_weights_scale_f32 = gemm1_weights_scale.to(torch.float32).contiguous()\n    gemm2_weights_scale_f32 = gemm2_weights_scale.to(torch.float32).contiguous()\n\n    if routing_bias is not None:\n        routing_bias = routing_bias.contiguous()\n\n    return trtllm_fp8_block_scale_moe(\n        routing_logits_f32,\n        routing_bias,\n        hidden_states.contiguous(),\n        hidden_states_scale_f32,\n        gemm1_weights.contiguous(),\n        gemm1_weights_scale_f32,\n        gemm2_weights.contiguous(),\n        gemm2_weights_scale_f32,\n        NUM_EXPERTS_GLOBAL,\n        TOP_K,\n        N_GROUP,\n        TOPK_GROUP,\n        INTERMEDIATE_SIZE,\n        local_expert_offset,\n        local_num_experts,\n        routed_scaling_factor,\n        routing_method_type=2,\n        use_shuffled_weight=False,\n    )\n"
+    }
+  ],
+  "description": "Solution using flashinfer.fused_moe.trtllm_fp8_block_scale_moe."
+}
diff --git a/workloads/gdn/gdn_decode_qk4_v8_d128_k_last.jsonl b/workloads/gdn/gdn_decode_qk4_v8_d128_k_last.jsonl
index 55238b47815043e9fda5475b0f13915ea416ec88..ed284caedd099674d44f82932055d40fe3ededcd 100644
--- a/workloads/gdn/gdn_decode_qk4_v8_d128_k_last.jsonl
+++ b/workloads/gdn/gdn_decode_qk4_v8_d128_k_last.jsonl
@@ -1,20 +1,54 @@
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diff --git a/workloads/gdn/gdn_prefill_qk4_v8_d128_k_last.jsonl b/workloads/gdn/gdn_prefill_qk4_v8_d128_k_last.jsonl
index 863d2d6a7f0758d969cbdea2d8ac53a5476c8ccc..b4b26dbd54ce711a266be89619d812e9638a9f5e 100644
--- a/workloads/gdn/gdn_prefill_qk4_v8_d128_k_last.jsonl
+++ b/workloads/gdn/gdn_prefill_qk4_v8_d128_k_last.jsonl
@@ -1,100 +1,100 @@
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